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ICS840001AKI-34 PDF预览

ICS840001AKI-34

更新时间: 2024-11-26 06:57:51
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
14页 697K
描述
Clock Generator, 213.33MHz, 3 X 3 MM, 0.95 MM HEIGHT, MO-220, VFQFN-16

ICS840001AKI-34 数据手册

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FEMTOCLOCKS™ CRYSTAL-TO-  
ICS840001I-34  
LVCMOS/LVTTL FREQUENCY SYNTHESIZER  
General Description  
Features  
The ICS840001I-34 is a two output LVCMOS/LVTTL  
Synthesizer and a member of the HiPerClocks  
family of high performance devices from IDT. One  
output is the LVCMOS/LVTTL main synthesized  
clock output (Q) and one output is a three-state  
Two LVCMOS/LVTTL outputs, 22typical output impedance  
One three-state reference clock output (REF_OUT)  
S
TM  
One main clock output (Q)  
IC  
HiPerClockS™  
Crystal oscillator interface can accept crystals from  
15.3125MHz to 42.67MHz, 18pF parallel resonant crystal  
LVCMOS/LVTTL reference clock (REF_OUT) output at the  
frequency of the crystal oscillator. The device can accept crystals  
from 15.3125MHz to 42.67MHz and can synthesize outputs from  
81.67MHz to 213.33MHz. The ICS840001I-34 is packaged in a  
3mm x 3mm 16-pin VFQFN, making it ideal for use on space  
constrained boards..  
Q output frequency range: 81.67MHz to 213.33MHz  
RMS phase jitter @106.25, (637kHz – 10MHz): 0.38ps (typical)  
VCO range: 490MHz to 640MHz  
Full 3.3V and 2.5V operating supply  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Common Application Configuration Table  
Inputs  
Output Frequency  
Crystal (MHz)  
M Divider  
VCO (MHz)  
N Divider  
(MHz)  
Application  
Serial Attached (SCSI),  
PCI Express, Processor Clock  
40  
15  
600  
6
100 (default)  
26.5625  
40  
24  
15  
24  
25  
25  
25  
32  
637.5  
600  
6
4
3
5
4
3
4
106.25  
150  
Fibre Channel  
Serial ATA (SATA), Processor Clock  
Fibre Channel 2  
Ethernet  
26.5625  
25  
637.5  
625  
212.5  
125  
25  
625  
156.25  
187.5  
155.52  
10 Gigabit Ethernet  
12 Gigabit Ethernet  
SONET  
22.5  
562.5  
622.08  
19.44  
Pin Assignment  
Block Diagram  
(Pullup)  
OE  
REF_OUT  
16 15 14 13  
1
2
3
OE  
XTAL_IN  
XTAL_OUT  
M0  
12  
11  
10  
Q
N-Div  
VDDO  
GND  
VDD  
XTAL_IN  
OSC  
VCO  
00 = ÷3  
01 = ÷4  
10 = ÷5  
Phase  
Detector  
Q
490MHz - 640MHz  
XTAL_OUT  
4
9
5
6
7
8
11 = ÷6 (default)  
M-Div  
11 = ÷15 (default)  
10 = ÷24  
ICS840001-34  
16 Lead VFQFN  
01 = ÷25  
3mm x 3mm x 0.95 package body  
K Package  
00 = ÷32  
(Pullup)  
M1  
(Pullup)  
M0  
Top View  
(Pullup)  
N1  
(Pullup)  
N0  
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER  
1
ICS840001I-34 REV. A FEBRUARY 15, 2007  

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