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ICS840002AGI

更新时间: 2024-11-25 11:14:35
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
13页 203K
描述
FEMTOCLOCKS? CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER

ICS840002AGI 数据手册

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ICS840002I  
FEMTOCLOCKS™ CRYSTAL-TO-  
LVCMOS/LVTTL FREQUENCY SYNTHESIZER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
Two LVCMOS outputs @ 3.3V, 17Ω typical output impedance  
The ICS840002I is a 2 output LVCMOS/LVTTL  
ICS  
Synthesizer optimized to generate Fibre Channel  
reference clock frequencies and is a member of  
the HiPerClocksTM family of high performance  
clock solutions from ICS. Using a 26.5625MHz  
• Selectable crystal oscillator interface  
or LVCMOS single-ended input  
HiPerClockS™  
• Output frequency range: 46.66MHz - 233.33MHz  
• VCO range: 560MHz - 700MHz  
18pF parallel resonant crystal, the following frequencies can be  
generated based on the 2 frequency select pins (F_SEL1:0):  
212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and  
53.125MHz.The ICS840002I uses ICS3rd generation low phase  
noise VCO technology and can achieve 1ps or lower typical  
rms phase jitter, easily meeting Fibre Channel jitter requirements.  
The ICS840002I is packaged in a 16-pin TSSOP package.  
• Supports the following output frequencies: 212.5MHz,  
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz  
• RMS phase jitter @ 212.5MHz (637KHz - 10MHz):  
0.83ps (typical)  
Typical phase noise at 212.5MHz:  
Offset  
Noise Power  
100Hz ............... -91.3 dBc/Hz  
1KHz ..............-114.3 dBc/Hz  
10KHz ..............-120.7 dBc/Hz  
100KHz ..............-120.2 dBc/Hz  
• Power supply modes:  
Core/Output  
3.3V/3.3V  
3.3V/2.5V  
2.5V/2.5V  
• -40°C to 85°C ambient operating temperature  
• Lead-Free package RoHS compliant  
FREQUENCY SELECT FUNCTION TABLE  
Inputs  
F_SEL1 F_SEL0 M Divider Value N Divider Value M/N Ratio Value  
Input Frequency  
(MHz)  
Output Frequency  
(MHz)  
26.5625  
26.5625  
26.5625  
26.5625  
26.04166  
0
0
1
1
0
0
1
0
1
1
24  
24  
24  
24  
24  
3
4
8
6
4
2
6
212.5  
159.375  
106.25  
53.125  
156.25  
6
12  
4
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Pullup  
OE  
1
2
3
4
5
6
7
8
F_SEL0  
nXTAL_SEL  
TEST_CLK  
OE  
MR  
nPLL_SEL  
VDDA  
16  
15  
14  
13  
12  
11  
10  
9
F_SEL1  
GND  
GND  
Q0  
Q1  
VDDO  
XTAL_IN  
XTAL_OUT  
2
Pullup:Pullup  
F_SEL1:0  
Pulldown  
nPLL_SEL  
Pulldown  
nXTAL_SEL  
26.5625MHz  
XTAL_IN  
VDD  
F_SEL1:0  
N
0
Q0  
Q1  
OSC  
1
0
ICS840002I  
16-LeadTSSOP  
4.4mm x 5.0mm x 0.92mm  
package body  
0 0 ÷3  
XTAL_OUT  
Pulldown  
0 1 ÷4  
Phase  
Detector  
1
TEST_CLK  
VCO  
1 0 ÷6  
1 1 ÷12 (default)  
G Package  
Top View  
M = ÷24 (fixed)  
Pulldown  
MR  
840002AGI  
www.icst.com/products/hiperclocks.html  
REV. A MARCH 10, 2005  
1

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