Datasheet > ICS83948I

ICS83948I

更新时间： 2024-11-25 11:14:35

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
10页	110K
描述
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

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ICS83948I 数据手册

ICS83948I

LOW SKEW, 1-TO-12

DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

Integrated

Circuit

Systems, Inc.

GENERAL DESCRIPTION

FEATURES

The ICS83948I is a low skew, 1-to-12 Differen-

• Twelve LVCMOS outputs

ICS

tial-to-LVCMOS Fanout Buffer and a member

of the HiPerClockS™ f a m ily of High Performance

Clock Solutions from ICS. The ICS83948I has

two selectable clock inputs. The CLK, nCLK

• Selectable LVCMOS clock or differential CLK, nCLK inputs

HiPerClockS™

• CLK, nCLK pair can accept the following differential

input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

pair can accept most standard differential input levels. The

LVCMOS_CLK can accept LVCMOS or LVTTL input levels.

The low impedance LVCMOS outputs are designed to drive

50Ω series or parallel terminated transmission lines. The

effective fanout can be increased from 12 to 24 by utilizing

the ability of the outputs to drive two series terminated lines.

• LVCMOS_CLK accepts the following input levels:

LVCMOS or LVTTL

• Maximum output frequency: 250MHz

• Output skew: 350ps (maximum)

• Part to part skew: 1.5ns (maximum)

• 3.3V core, 3.3V output

The ICS83948I is characterized at 3.3V core/3.3V output.

Guaranteed output and part-to-part skew characteristics

make the ICS83948I ideal for those clock distribution ap-

plications demanding well defined performance and re-

peatability.

• -40°C to 85°C ambient operating temperature

• Available in both standard and lead-free RoHS-compliant

packages

BLOCK DIAGRAM

PIN ASSIGNMENT

CLK_EN

32 31 30 29 28 27 26 25

LVCMOS_CLK

GND

CLK_SEL

LVCMOS_CLK

CLK

nCLK

V^DDO

Q10

Q11

nCLK

CLK_SEL

ICS83948I

GND

CLK_EN

V^DDO

V^DD

GND

10 11 12 13 14 15 16

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

TopView

83948AYI

www.icst.com/products/hiperclocks.html

REV.C DECEMBER 15, 2005

12 3 4 5 6 7...10

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