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ICS840001-34 PDF预览

ICS840001-34

更新时间: 2024-11-25 11:14:35
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
9页 165K
描述
FEMTOCLOCKS? CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER

ICS840001-34 数据手册

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PRELIMINARY  
ICS840001-34  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ CRYSTAL-TO-  
LVCMOS/LVTTL FREQUENCY SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
The ICS840001-34 is a two output LVCMOS/ (2) LVCMOS/LVTTL outputs, 20Ω typical output impedence  
ICS  
LVTTL Synthesizer and a member of the  
HiPerClocksTM family of high performance  
devices from ICS. One output is the LVCMOS/  
LVTTL main synthesized clock output (Q) and  
(1) Main clock output (Q)  
(1)Three-state reference clock output (REF_CLK)  
HiPerClockS™  
Crystal oscillator interface can accept crystals from  
15.3125MHz to 42.67MHz, 18pF parallel resonant crystal  
one output is a three-state LVCMOS/LVTTL reference  
clock (REF_CLK) output at the frequency of the crystal  
oscillator. The device can accept crystal from 15.3125MHz  
to 42.67MHz and can synthesize outputs from 81.67MHz  
to 213.33MHz.The ICS840001-34 has excellent <1ps  
phase jitter performance over the 637kHz – 10MHz  
integration range. The ICS840001-34 is packaged in a  
3mm x 3mm 16-pin VFQFN, making it ideal for use on  
space constrained boards.  
Output frequency range: 81.67MHz to 213.33MHz  
VCO range: 490MHz to 640MHz  
RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal  
(637kHz - 10MHz): 0.38ps (typical)  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
COMMON APPLICATION CONFIGURATION TABLE  
Inputs  
Output Frequency  
Application  
Serial Attached (SCSI),  
(MHz)  
Crystal  
M Divider  
VCO (MHz)  
N Divider  
40  
15  
600  
6
100  
PCI Express™, Processor Clock  
26.5625  
40  
24  
15  
24  
25  
25  
25  
32  
637.5  
600  
6
4
3
5
4
3
4
106.25  
150  
Fibre Channel  
Serial ATA (SATA), Processor Clock  
Fibre Channel 2  
26.5625  
25  
637.5  
625  
212.5  
125  
Ethernet  
25  
625  
156.25  
187.5  
155.52  
10 Gigabit Ethernet  
12 Gigabit Ethernet  
SONET  
22.5  
562.5  
622.08  
19.44  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
(Pullup)  
OE  
REF_CLK  
16 15 14 13  
OE  
XTAL_IN  
XTAL_OUT  
M0  
1
2
3
4
12  
Q
11 VDDO  
00 = ÷3  
VCO  
XTAL_IN  
OSC  
XTAL_OUT  
Phase  
Detector  
01 = ÷4  
GND  
VDD  
10  
9
Q
490MHz - 640MHz  
10 = ÷5  
11 = ÷6 (default)  
5
6
7
8
11 = ÷15 (default)  
10 = ÷24  
01 = ÷25  
00 = ÷32  
ICS840001-34  
16-Lead VFQFN  
3mm x 3mm x 0.95 package body  
K Package  
(Pullup)  
M1  
Top View  
(Pullup)  
M0  
(Pullup)  
N1  
(Pullup)  
N0  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
840001AK-34  
www.icst.com/products/hiperclocks.html  
REV. A MAY 6, 2005  
1

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