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ICS839893AYIT PDF预览

ICS839893AYIT

更新时间: 2024-11-25 04:02:35
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
10页 141K
描述
LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER

ICS839893AYIT 数据手册

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ICS839893I  
LOW SKEW, 1-TO-13  
LVCMOS/LVTTL BUFFER DIVIDER  
Integrated  
Circuit  
Systems, Inc.  
FEATURES  
GENERAL DESCRIPTION  
• 13 LVCMOS/LVTTL outputs: 3 banks (6, 6, 1 outputs per  
bank respectively)  
The ICS839893I is a high-performance one to  
ICS  
HiPerClockS™  
thirteen LVCMOS/LVTTL buffer/divider and is  
a member of the HiPerClockS™ family of High  
Performance Clock Solutions from ICS. The  
device has two selectable LVCMOS/LVTTL  
• Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs  
• CLK0, CLK1 supports the following input types:  
LVCMOS, LVTTL  
clock inputs and it generates 13 new LVCMOS/LVTTL clock  
outputs.The first bank of six outputs offers divide-by-1, 2, 4,  
8 or 16.The second bank of six outputs can be configured to  
the same divide ratio as the first bank, or with an additional  
divide-by-two.The first two banks can be placed into a high-  
impedance output state with the assertion of a LOW on the  
nOE/MR input. One additional output can be configured  
to divide-by-4, 6, 8 or 16. This device is functional with full  
3.3V or full 2.5V supplies.  
• Maximum output frequency: 250MHz  
• Output skew: 40ps (maximum), within bank  
• Full 3.3V or 2.5V operating supply  
• -40°C to 85°C ambient operating temperature  
• Available in both, Standard and RoHS/Lead-Free compliant  
packages  
SIMPLIFIED BLOCK DIAGRAM  
PIN ASSIGNMENT  
nOE/MR  
F
FSEL0 FSEL1
FSEL2QA  
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷1  
÷2  
÷2  
÷4  
÷2  
36 35 34 33 32 31 30 29 28 27 26 25  
CLK0  
CLK1  
0
0
0
1
1
1
1
0
1
GND  
QA0  
37  
38  
39  
40  
41  
42  
43  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
GND  
QB0  
QA0:QA5  
QB0:QB5  
D Q  
D Q  
QA1  
QB1  
÷16  
÷8  
VDDO_A  
GND  
QA2  
VDDO_B  
GND  
QB2  
ICS839893I  
48-Pin LQFP  
7mm x 7mm x 1.4mm  
body package  
REF_SEL  
÷4  
0
1
QA3  
QB3  
÷
2
VDDO_A  
GND  
QA4  
44  
45  
46  
VDDO_B  
GND  
QB4  
Y Package  
Top View  
FSEL0 FSEL1 FSEL2 QC  
0
0
0
÷8  
QA5  
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
÷8  
÷6  
47  
48  
1
QB5  
VDDO_A  
VDDO_B  
QC  
÷8  
D Q  
2 3 4 5 6 7 8 9 10 11 12  
÷4  
÷16  
÷8  
÷4  
FSEL[0:2]  
FSEL3  
839893AYI  
www.icst.com/products/hiperclocks.html  
REV.A AUGUST 8, 2005  
1

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