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ICS8304M-01T PDF预览

ICS8304M-01T

更新时间: 2024-11-02 15:34:35
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
11页 106K
描述
Low Skew Clock Driver, 0 True Output(s), 4 Inverted Output(s), PDSO8, 3.80 X 4.80 MM, 1.47 MM HEIGHT, MS-012, SOIC-8

ICS8304M-01T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.74输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:4
端子数量:8实输出次数:
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240传播延迟(tpd):3.6 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.05 ns
座面最大高度:1.75 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
最小 fmax:166 MHzBase Number Matches:1

ICS8304M-01T 数据手册

 浏览型号ICS8304M-01T的Datasheet PDF文件第2页浏览型号ICS8304M-01T的Datasheet PDF文件第3页浏览型号ICS8304M-01T的Datasheet PDF文件第4页浏览型号ICS8304M-01T的Datasheet PDF文件第5页浏览型号ICS8304M-01T的Datasheet PDF文件第6页浏览型号ICS8304M-01T的Datasheet PDF文件第7页 
ICS8304-01  
LOW SKEW, 1-TO-4  
LVCMOS / LVTTL INVERTING FANOUT BUFFER  
Integrated  
Circuit  
Systems, Incꢀ  
GENERAL DESCRIPTION  
FEATURES  
The ICS8304-01 is a low skew, 1-to-4 Invert- 4 LVCMOS / LVTTL outputs  
,&6  
ing Fanout Buffer and a member of the  
HiPerClockS™ family of High Performance  
Clock Solutions from ICS. The ICS8304-01  
is characterized at full 3.3V for input VDD, and  
LVCMOS clock input  
HiPerClockS™  
Output frequency: 166MHz  
Output skew: 50ps (maximum)  
mixed 3.3V and 2.5V for output operating supply modes  
(VDDO). Guaranteed output and part-to-part skew char-  
acteristics make the ICS8304-01 ideal for those clock  
distribution applications demanding well defined per-  
formance and repeatability.  
Part-to-part skew: 600ps (maximum)  
Small 8 lead SOIC package saves board space  
3.3V input, outputs may be either 3.3V or 2.5V supply modes  
0°C to 70°C ambient operating temperature  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
nQ0  
VDDO  
VDD  
nQ3  
nQ2  
nQ1  
nQ0  
1
2
3
4
8
7
6
5
CLK  
GND  
nQ1  
CLK  
nQ2  
ICS8304-01  
8-Lead SOIC  
3.8mm x 4.8mm x 1.47mm package body  
nQ3  
M Package  
Top View  
8304AM-01  
www.icst.com/products/hiperclocks.html  
REV. C JUNE 17, 2002  
1

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