LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
ICS8305
General Description
Features
The ICS8305 is a low skew, 1-to-4, Differential/
• Four LVCMOS / LVTTL outputs, 7Ω output impedance
S
IC
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a
member of the HiPerClockS™family of High
Performance Clock Solutions from IDT. The
ICS8305 has selectable clock inputs that accept
• Selectable differential or LVCMOS / LVTTL clock inputs
HiPerClockS™
• CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
• LVCMOS_CLK supports the following input types: LVCMOS,
either differential or single ended input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock enable
pin. Outputs are forced LOW when the clock is disabled. A
separate output enable pin controls whether the outputs are in the
active or high impedance state.
LVTTL
• Maximum output frequency: 350MHz
• Output skew: 35ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Additive phase jitter, RMS: 0.04ps (typical)
Guaranteed output and part-to-part skew characteristics make the
ICS8305 ideal for those applications demanding well defined
performance and repeatability.
• Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
3.3V/1.5V
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
GND
OE
VDD
1
2
16 Q0
Pullup
CLK_EN
D
15
VDDO
Q1
GND
Q2
Q
14
13
3
4
LE
CLK_EN
CLK
nCLK
Pulldown
LVCMOS_CLK
0
0
12
11
10
9
5
6
7
8
Q0
Pulldown
Pullup/
Pulldown
VDDO
Q3
CLK
nCLK
1
1
CLK_SEL
LVCMOS_CLK
GND
Q1
Q2
Q3
Pullup
Pullup
CLK_SEL
ICS8305
16-Lead TSSOP
4.4mm x 3.0mm x 0.925mm
package body
G Package
OE
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
1
ICS8305AG REV. C OCTOBER 23, 2008