Datasheet > ICS83052AGILF

ICS83052AGILF

更新时间： 2024-11-02 04:44:19

品牌	Logo	应用领域
矽成 - ICSI		复用器逻辑集成电路光电二极管
页数	文件大小	规格书
12页	170K
描述
2:1, SINGLE-ENDED MULTIPLEXER

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ICS83052AGILF 数据手册

ICS83052I

Integrated

Circuit

Systems, Inc.

2:1, SINGLE-ENDED MULTIPLEXER

TABLE 1. PIN DESCRIPTIONS

Number

Name

V_DDO

Type

Description

Power

Input

Output supply pin.

Power supply ground.

GND

3, 6

CLK1, CLK0

V_DD

Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.

Core supply pin.

Power

Output enable. When LOW, outputs are in HIGH impedance state.

When HIGH, outputs are active. LVCMOS / LVTTL interface levels.

Input

Pullup

Clock select input. See Control Input Function Table.

LVCMOS / LVTTL interface levels.

SEL0

Input

Pulldown

Output

Single-ended clock output. LVCMOS/LVTTL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Units

Symbol Parameter

Test Conditions

Minimum Typical Maximum

C_IN

Input Capacitance

Input Pullup Resistor

R_PULLUP

kΩ

R_PULLDOWNInput Pulldown Resistor

V_DDO= 3.465V

V_DDO= 2.625V

Power Dissipation Capacitance

(per output)

C_PD

V_DDO= 1.89V

R_OUT

Output Impedance

TABLE 3. CONTROL INPUT FUNCTION TABLE

Control Inputs

Input Selected to Q

SEL0

CLK0

CLK1

83052AGI

www.icst.com/products/hiperclocks.html

REV.A AUGUST 2, 2005

12 3 4 5 6 7...12

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