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ICS527R-01I PDF预览

ICS527R-01I

更新时间: 2024-11-05 22:11:19
品牌 Logo 应用领域
矽成 - ICSI 时钟
页数 文件大小 规格书
8页 116K
描述
Clock Slicer⑩ User Configurable Zero Delay Buffer

ICS527R-01I 数据手册

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ICS527-01  
Clock Slicer™  
User Configurable Zero Delay Buffer  
Description  
Features  
• Packaged as 28 pin SSOP (150 mil body)  
• Synchronizes fractional clocks rising edges  
• User determines the output frequency - no  
software needed  
The ICS527-01 Clock Slicer™ is the most flexible  
way to generate an output clock from an input  
clock with zero skew. The user can easily configure  
the device to produce nearly any output clock that  
is multiplied or divided from the input clock. The  
part supports non-integer multiplications and  
divisions. A SYNC pulse indicates the rising clock  
edges that are aligned with zero skew. Using  
Phase-Locked Loop (PLL) techniques, the device  
accepts an input clock up to 200 MHz and  
• Slices frequency or period  
• SYNC pulse output indicates aligned edges  
• Input clock frequency of 600 kHz - 200 MHz  
• Output clock frequencies up to 160 MHz  
• Very low jitter  
produces an output clock up to 160 MHz.  
The ICS527-01 aligns rising edges on ICLK and  
FBIN at a ratio determined by the reference and  
feedback dividers.  
• Duty cycle of 45/55 up to 160 MHz  
• Operating voltage of 3.3 V (±10%)  
• Pin selectable double drive strength  
• Multiple outputs available when combined with  
Buffalo clock drivers  
For configurable clocks that do not require  
zero delay, use the ICS525.  
• Zero input to output skew  
• Industrial temperature version available  
• Advanced, low power CMOS process  
Block Diagram  
S1:S0  
2
2XDRIVE  
R6:R0  
7
PDTS  
Reference  
Divide  
CLK1  
CLK2  
ICLK  
PLL  
PDTS  
Feedback  
Divide  
FBIN  
÷2  
1
0
SYNC  
7
DIV2  
PDTS  
OECLK2  
External feedback from CLK1 or CLK2 (not both).  
1
F6:F0  
MDS 527-01 B  
Revision 020801  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126•(408)295-9800tel • www.icst.com  

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