Datasheet > ICS527R-03T

ICS527R-03T

更新时间： 2024-11-09 11:14:27

品牌	Logo	应用领域
矽成 - ICSI		时钟
页数	文件大小	规格书
8页	163K
描述
Clock Slicer User Configurable PECL Output Zero Delay Buffer

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ICS527R-03T 数据手册

P r e l i m i n a r y I n f o r m a t i o n

ICS527-03

Clock Slicer User Configurable PECL Output Zero Delay Buffer

Description

Features

The ICS527-03 is the most flexible way to generate an

output clock from an input clock with zero skew. The

user can easily configure the device to produce nearly

any output clock that is multiplied or divided from the

input clock. The part supports non-integer

multiplications and divisions. Using Phase-Locked

Loop (PLL) techniques, the device accepts an input

clock up to 200 MHz and produces an output clock up

to 160 MHz.

• Packaged as 28 pin SSOP (150 mil body)

• Synchronizes fractional clocks rising edges

• CMOS in to PECL out

• Pin selectable dividers

• Zero input to output skew

• User determines the output frequency - no software

needed

• Slices frequency or period

• Input clock frequency of 1.5 MHz to 200 MHz

• Output clock frequencies from 2.5 MHz to 160 MHz

• Very low jitter

The ICS527-03 aligns rising edges on CLKIN with

FBPECL at a ratio determined by the reference and

feedback dividers.

• Duty cycle of 45/55

• Operating voltage of 3.3 V

For a PECL input and output clock with zero delay, use

the ICS527-04.

• Advanced, low power CMOS process

Block Diagram

R6:R0

VDD

68 ohm

Divide

by 2

Reference

Divider

CLKIN

PECL

180 ohm

Phase Comparator,

Charge Pump, and

Loop Filter

Output

Divider

VCO

VDD

Divide

by 2

68 ohm

FBPECL

Feedback

Divider

PECL

180 ohm

GND

DIV2

PDTS

F6:F0

S1:S0

MDS 527-03 B

Revision 122804

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

12 3 4 5 6 7 8

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与ICS527R-03T相关器件

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