Datasheet > IBM13M16734BCD-360T

IBM13M16734BCD-360T

更新时间： 2024-10-29 20:27:47

品牌	Logo	应用领域
国际商业机器公司 - IBM		时钟动态存储器内存集成电路
页数	文件大小	规格书
20页	538K
描述
Synchronous DRAM Module, 16MX72, 7.2ns, CMOS, DIMM-168

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IBM13M16734BCD-360T 技术参数

生命周期：	Obsolete	零件包装代码：	DIMM
包装说明：	DIMM, DIMM168	针数：	168
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.36	风险等级：	5.84
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	7.2 ns
最大时钟频率 (fCLK)：	100 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-XDMA-N168	内存密度：	1207959552 bit
内存集成电路类型：	SYNCHRONOUS DRAM MODULE	内存宽度：	72
功能数量：	1	端口数量：	1
端子数量：	168	字数：	16777216 words
字数代码：	16000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	16MX72	输出特性：	3-STATE
封装主体材料：	UNSPECIFIED	封装代码：	DIMM
封装等效代码：	DIMM168	封装形状：	RECTANGULAR
封装形式：	MICROELECTRONIC ASSEMBLY	电源：	3.3 V
认证状态：	Not Qualified	刷新周期：	4096
最大待机电流：	0.033 A	子类别：	DRAMs
最大压摆率：	2.645 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

IBM13M16734BCD-360T 数据手册

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IBM13M16734BCD

16M x 72 1 Bank Registered/Buffered SDRAM Module

Features

• 168-Pin Registered 8-Byte Dual In-Line Memory

Module

2, 3 (Buffered mode)

- Burst Type: Sequential or Interleave

• 16Mx72 Synchronous DRAM DIMM

• Performance:

- Burst Length: 1, 2, 4, 8, Full-Page (Full-

Page supports Sequential burst only)

- Operation: Burst Read and Write

-10 -260 -360 -360 Units

Device Latency

Clock Frequency

or Multiple Burst Read with Single Write

• Data Mask for Byte Read/Write control

• Auto Refresh (CBR) and Self Refresh

• Automatic and controlled Precharge Commands

• Suspend Mode and Power Down Mode

• 12/10/2 Addressing (Row/Column/Bank)

• 4096 refresh cycles distributed across 64ms

• Card size: 5.25" x 0.157" x 1.70"

100 100 100 MHz

7.2 10.2 7.2 ns

Clock Access Time 8.2

• Intended for 66/100MHz and PC100 applica-

tions

• Inputs and outputs are LVTTL (3.3V) compatible

• Single 3.3V ± 0.3V Power Supply

• Single Pulsed RAS interface

• SDRAMs have four internal banks

• Module has one physical bank

• Fully Synchronous to positive Clock Edge

• Programmable Operation:

• Gold contacts

• SDRAMS in TSOP - Type II Package

• Serial Presence Detect with Write protect feature

- DIMM CAS Latency:3, 4 (Registered mode),

Description

IBM13M16734BCD is a registered 168-Pin Synchro-

nous DRAM Dual In-Line Memory Module (DIMM)

organized as a 16Mx72 high-speed memory array.

The DIMM uses eighteen 16Mx4 SDRAMs in 400

mil TSOP packages. The DIMM achieves high-

speed data-transfer rates of up to 100 MHz by

employing a prefetch/pipeline hybrid architecture

that synchronizes the output data to a system clock.

(CK0 is connected to the PLL, and CK1, CK2, and

CK3 are terminated on the DIMM.) A single clock

enable (CKE0) controls all devices on the DIMM,

enabling the use of SDRAM power-down modes.

Prior to any access operation, the device CAS

latency and burst type/length/operation type must be

programmed into the DIMM by address inputs A0-A9

using the mode register set cycle. The DIMM CAS

latency when operated in buffered mode is the same

as the device CAS latency as specified in the SPD

EEPROM. The DIMM CAS latency when operated in

registered mode is one clock later due to the

address and control signals being clocked to the

SDRAM devices.

The DIMM is intended for use in applications operat-

ing from 66MHz to 100 MHz, PC100, memory bus

speeds, and/or heavily loaded bus applications. All

control and address signals are re-driven through

registers/buffers to the SDRAM devices. The DIMM

can be operated in either registered mode (REGE

pin tied high), where the control/address input sig-

nals are latched in the register on one rising clock

edge and sent to the SDRAM devices on the follow-

ing rising clock edge (data access is delayed by one

clock), or in buffered mode (REGE pin tied low)

where the input signals pass through the regis-

ter/buffer to the SDRAM devices on the same clock.

XTK simulation models of the DIMM are available to

determine which mode to design for.

The DIMM uses serial presence detects imple-

mented via a serial EEPROM using the two-pin IIC

protocol. The first 128 bytes of serial PD data are

programmed and locked by the DIMM manufacturer.

The last 128 bytes are available to the customer and

may be write protected by providing a high level to

pin 81 on the DIMM. An on-board pulldown resistor

keeps this in the write-enable mode.

All IBM 168-pin DIMMs provide a high-performance,

flexible 8-byte interface in a 5.25" long space-saving

footprint.

A phase-lock loop (PLL) on the DIMM is used to re-

drive the clock signals to both the SDRAM devices

and the registers to minimize system clock loading.

19L7292.E93875A

8/99

Use is further subject to the provisions at the end of this document.

Page 1 of 20

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与IBM13M16734BCD-360T相关器件

型号	品牌	获取价格	描述	数据表
IBM13M16734JCA-260T	ETC	获取价格	x72 SDRAM Module
IBM13M16734JCA-360T	ETC	获取价格	x72 SDRAM Module
IBM13M16734JCB-75AT	ETC	获取价格	x72 SDRAM Module
IBM13M32734BCA-10Y	IBM	获取价格	Synchronous DRAM Module, 32MX72, 10.7ns, CMOS, PDMA168
IBM13M32734BCA-322Y	IBM	获取价格	Synchronous DRAM Module, 32MX72, 7.7ns, CMOS, PDMA168
IBM13M32734BCB-75AY	ETC	获取价格	x72 SDRAM Module
IBM13M32734BCC-365Y	IBM	获取价格	Synchronous DRAM Module, 32MX72, 6.5ns, CMOS, DIMM-168
IBM13M32734BCC-365Z	IBM	获取价格	Synchronous DRAM Module, 32MX72, 6.5ns, CMOS, DIMM-168
IBM13M32734BCC-370Y	IBM	获取价格	Synchronous DRAM Module, 32MX72, 7ns, CMOS, DIMM-168
IBM13M32734BCC-370Z	IBM	获取价格	Synchronous DRAM Module, 32MX72, 7ns, CMOS, DIMM-168

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