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IBM13M16734JCB-75AT PDF预览

IBM13M16734JCB-75AT

更新时间: 2024-10-28 23:57:39
品牌 Logo 应用领域
其他 - ETC 内存集成电路动态存储器时钟
页数 文件大小 规格书
22页 341K
描述
x72 SDRAM Module

IBM13M16734JCB-75AT 数据手册

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IBM13M16734JCB  
16M x 72 One-Bank Registered / Buffered SDRAM Module  
Features  
• 168-Pin Registered 8-Byte Dual In-Line Memory  
Module  
• 16Mx72 Synchronous DRAM DIMM  
• Performance:  
• Programmable Operation:  
- DIMM CAS Latency:4 (Registered mode)  
- Burst Type: Sequential or Interleave  
- Burst Length: 1, 2, 4, 8, Full-Page  
- Operation: Burst Read and Write  
-75A Reg.  
Units  
DIMM CAS Latency  
f
4
or Multiple Burst Read with Single Write  
• Data Mask for Byte Read/Write control  
• Auto Refresh (CBR) and Self Refresh  
• Automatic and controlled Precharge Commands  
• Suspend Mode and Power Down Mode  
• 12/10/2 Addressing (Row/Column/Bank)  
• 4096 refresh cycles distributed across 64ms  
• Card size: 5.25" x 1.5" x 0.157"  
Clock Frequency  
133  
7.5  
MHz  
ns  
CK  
CK  
AC  
t
t
Clock Cycle  
Clock Access Time  
5.65  
ns  
• Intended for 133MHz applications  
• Inputs and outputs are LVTTL (3.3V) compatible  
• Single 3.3V ± 0.3V Power Supply  
• Single Pulsed RAS interface  
• SDRAMs have four internal banks  
• Module has one physical bank  
• Gold contacts  
• SDRAMS in TSOP - Type II Package  
• Serial Presence Detect with Write protect feature  
• Fully Synchronous to positive Clock Edge  
Description  
IBM13M16734JCB is a registered 168-Pin Synchro-  
nous DRAM Dual In-Line Memory Module (DIMM)  
organized as a 16Mx72 high-speed memory array.  
The DIMM uses nine 16Mx8 SDRAMs in 400 mil  
TSOP packages. The DIMM achieves high-speed  
data-transfer rates of 133MHz by employing a  
prefetch/pipeline hybrid architecture that synchro-  
nizes the output data to a system clock.  
trols all devices on the DIMM, enabling the use of  
SDRAM power-down modes.  
Prior to any access operation, the device CAS  
latency and burst type/length/operation type must  
be programmed into the DIMM by address inputs  
A0-A9, I/O addresses BA0 and BA1 using the mode  
register set cycle. The DIMM CAS latency, when  
operated in Registered mode, is one clock later than  
the device CAS latency due to the address and con-  
trol signals being clocked to the SDRAM devices.  
The DIMM is intended for use in applications oper-  
ating at 133MHz memory bus speed. All control and  
address signals are re-driven through registers/buff-  
ers to the SDRAM devices. Operating in registered  
mode (REGE pin tied high), the control/address  
input signals are latched in the register on one rising  
clock edge and sent to the SDRAM devices on the  
following rising clock edge (data access is delayed  
by one clock).  
The DIMM uses serial presence detects imple-  
mented via a serial EEPROM using the two-pin IIC  
protocol. The first 128 bytes of serial PD data are  
programmed and locked by the DIMM manufac-  
turer. The last 128 bytes are available to the cus-  
tomer and may be write protected by providing a  
high level to pin 81 on the DIMM. An on-board pull-  
down resistor keeps this in the write-enable mode.  
A phase-lock loop (PLL) on the DIMM is used to re-  
drive the clock signals to the SDRAM devices to  
minimize system clock loading. (CK0 is connected  
to the PLL, and CK1, CK2, and CK3 are terminated  
on the DIMM.) A single clock enable (CKE0) con-  
All IBM 168-pin DIMMs provide a high-performance,  
flexible 8-byte interface in a 5.25" long space-saving  
footprint.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
06K7739.H03380  
4/00  
Page 1 of 22  

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