Datasheet > IBM13M64734CCA-75AY

IBM13M64734CCA-75AY

更新时间： 2024-10-29 20:09:11

品牌	Logo	应用领域
国际商业机器公司 - IBM		时钟动态存储器内存集成电路
页数	文件大小	规格书
20页	383K
描述
Synchronous DRAM Module, 64MX72, 5.65ns, CMOS, DIMM-168

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IBM13M64734CCA-75AY 技术参数

生命周期：	Obsolete	零件包装代码：	DIMM
包装说明：	DIMM, DIMM168	针数：	168
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.36	风险等级：	5.84
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	5.65 ns
其他特性：	AUTO/SELF REFRESH	最大时钟频率 (fCLK)：	133 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-XDMA-N168
内存密度：	4831838208 bit	内存集成电路类型：	SYNCHRONOUS DRAM MODULE
内存宽度：	72	功能数量：	1
端口数量：	1	端子数量：	168
字数：	67108864 words	字数代码：	64000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	64MX72
输出特性：	3-STATE	封装主体材料：	UNSPECIFIED
封装代码：	DIMM	封装等效代码：	DIMM168
封装形状：	RECTANGULAR	封装形式：	MICROELECTRONIC ASSEMBLY
电源：	3.3 V	认证状态：	Not Qualified
刷新周期：	4096	自我刷新：	YES
最大待机电流：	0.051 A	子类别：	DRAMs
最大压摆率：	7.15 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

IBM13M64734CCA-75AY 数据手册

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IBM13M64734CCA

64M x 72 2-Bank Registered SDRAM Module

Features

• 168-Pin Registered 8-Byte Dual In-Line Memory

Module

• 64Mx72 Synchronous DRAM DIMM

• Programmable operation:

- DIMM CAS Latency: 4 (Registered mode);

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, 8, and Full-Page

- Operation: Burst Read and Write or Multiple

Burst Read with Single Write

-75A

Reg.

Units

• Data Mask for Byte Read/Write control

• Auto Refresh (CBR) and Self Refresh

• Automatic and controlled Precharge commands

• Suspend mode and Power Down mode

• 12/11/2 Addressing (Row/Column/Bank)

• 4096 refresh cycles distributed across 64ms

• Card size: 5.25" x 1.70" x 0.320"

• Gold contacts

DIMM CAS Latency

Clock Frequency

Clock Cycle

133

7.5

100

10.0

5.65

MHz

Clock Access Time

5.65

• Intended for 100MHz and 133MHz applications

• Inputs and outputs are LVTTL (3.3V) compatible

• Single 3.3V ± 0.3V power supply

• DRAMs in TSOJ - 2 High Package

• Serial Presence Detect with Write protect fea-

ture

• Single Pulsed RAS interface

• SDRAMs have four internal banks

• Module has two physical banks

• Fully synchronous to positive clock edge

Description

IBM13M64734CCA is a registered 168-Pin Syn-

chronous DRAM Dual In-Line Memory Module

(DIMM) organized as a 64Mx72 high-speed memory

array. The DIMM uses 18 64Mx4 SDRAMs in 400

mil TSOJ stacked packages. The DIMM achieves

high-speed data-transfer rates of 100MHz and

133MHz by employing a prefetch/pipeline hybrid

architecture that synchronizes the output data to a

system clock.

enable (CKE0) controls all devices on the DIMM,

enabling the use of SDRAM Power Down modes;

the stacked devices share a common CKE pin.

Prior to any access operation, the device CAS

latency and burst type/length/operation type must

be programmed into the DIMM by address inputs

A0-A13 using the mode register set cycle. The

DIMM CAS latency when operated in Registered

mode is one clock later than the device CAS latency

due to the address and control signals being

clocked to the SDRAM devices.

The DIMM is intended for use in applications operat-

ing at 100Mhz and 133MHz memory bus speeds. All

control and address signals are re-driven through

registers/buffers to the SDRAM devices. Operating

in registered mode (REGE pin tied high), the con-

trol/address input signals are latched in the register

on one rising clock edge and sent to the SDRAM

devices on the following rising clock edge (data

access is delayed by one clock).

The DIMM uses serial presence detects imple-

mented via a serial EEPROM using the two-pin IIC

protocol. The first 128 bytes of serial PD data are

programmed and locked by the DIMM manufac-

turer. The last 128 bytes are available to the cus-

tomer and may be write protected by providing a

high level to pin 81 on the DIMM. An on-board pull-

down resistor keeps this in the Write Enable mode.

A phase-lock loop (PLL) on the DIMM is used to re-

drive the clock signals to both the SDRAM devices

and the registers to minimize system clock loading.

(CK0 is connected to the PLL, and CK1, CK2, and

CK3 are terminated on the DIMM). A single clock

All IBM 168-pin DIMMs provide a high-performance,

flexible 8-byte interface in a 5.25" long space-saving

footprint.

Use is further subject to the provisions at the end of this document.

19L7317.E92596

8/99

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与IBM13M64734CCA-75AY相关器件

型号	品牌	获取价格	描述	数据表
IBM13M64734HCA-260T	ETC	获取价格	x72 SDRAM Module
IBM13M64734HCA-360T	ETC	获取价格	x72 SDRAM Module
IBM13M64734HCA-75AT	ETC	获取价格	x72 SDRAM Module
IBM13M8734HCB-10T	IBM	获取价格	DRAM Module, 8MX72, 8ns, CMOS, DIMM-168
IBM13M8734HCB-360T	IBM	获取价格	DRAM Module, 8MX72, 6ns, CMOS, DIMM-168
IBM13M8734HCB-365T	IBM	获取价格	DRAM Module, 8MX72, 6.5ns, CMOS, DIMM-168
IBM13M8734HCB-370T	IBM	获取价格	DRAM Module, 8MX72, 7ns, CMOS, DIMM-168
IBM13M8734HCB-75AT	ETC	获取价格	x72 SDRAM Module
IBM13M8734HCC-10T	ETC	获取价格	x72 SDRAM Module
IBM13M8734HCC-260T	ETC	获取价格	x72 SDRAM Module

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