Datasheet > IBM13N16734JCA-360T

IBM13N16734JCA-360T

更新时间： 2024-10-28 23:57:39

品牌	Logo	应用领域
其他 - ETC		内存集成电路动态存储器时钟
页数	文件大小	规格书
18页	321K
描述
x72 SDRAM Module

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IBM13N16644JCA

IBM13N16734JCA

16M x 64/72 One-Bank Unbuffered SDRAM Module

Features

• 168-Pin Unbuffered 8-Byte Dual In-Line Memory

Module

• Programmable Operation:

- CAS Latency: 2, 3

• Intended for PC100 applications

• Clock Frequency: 100MHz

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, 8, Full-Page

(Full-Page supports Sequential burst only)

- Operation: Burst Read and Write or Multiple

Burst Read with Single Write

• Clock Cycle: 10.0ns

• -260 and -360 speed sorts

• Inputs and outputs are LVTTL (3.3V) compatible

• Single 3.3V ± 0.3V Power Supply

• Single Pulsed RAS interface

• SDRAMs have four internal banks

• Module has one physical bank

• Fully Synchronous to positive Clock Edge

• Data Mask for Byte Read/Write control

• Auto Refresh (CBR) and Self Refresh

• Automatic and controlled Precharge commands

• Suspend Mode and Power Down Mode

• 12/10/2 Addressing (Row/Column/Bank)

• 4096 Refresh cycles distributed across 64ms

• Card size: 5.25" x 1.375" x 0.106"

• Gold contacts

• SDRAMs in TSOP Type II Package

• Serial Presence Detect with Write Protect

Description

IBM13N16644JCA / IBM13N16734JCA are unbuf-

fered 168-pin Synchronous DRAM Dual In-Line

Memory Modules (DIMMs) which are organized as

16Mx64 and 16Mx72 high-speed memory arrays

and are configured as one 16M x 64/72 physical

bank. The DIMMs use eight (16Mx64) or nine

(16Mx72) 16Mx8 SDRAMs in 400mil TSOP II pack-

ages. The DIMMs achieve high-speed data transfer

rates of up to 100MHz by employing a prefetch/pipe-

line hybrid architecture that supports the JEDEC 1N

rule while allowing very low burst power.

for each operation. A 14-bit address bus accepts

address information in a row/column multiplexing

arrangement.

Prior to any Access operation, the CAS latency,

burst type, burst length, and Burst operation type

must be programmed into the DIMM by address

inputs A0-A9 during the Mode Register Set cycle.

The DIMM uses serial presence detects imple-

mented via a serial EEPROM using the two-pin IIC

protocol. The first 128 bytes of serial PD data are

used by the DIMM manufacturer. The last 128 bytes

are available to the customer.

All control, address, and data input/output circuits

are synchronized with the positive edge of the exter-

nally supplied clock inputs.

All IBM 168-pin DIMMs provide a high-performance,

flexible 8-byte interface in a 5.25" long space-saving

footprint. Related products include both EDO DRAM

and SDRAM unbuffered DIMMs in both non-parity

x64 and ECC-Optimized x72 configurations.

All inputs are sampled at the positive edge of each

externally supplied clock (CK0, CK2). Internal oper-

ating modes are defined by combinations of RAS,

CAS, WE, S0/S2, DQMB, and CKE0 signals. A

command decoder initiates the necessary timings

Card Outline

(Front)

(Back)

10 11

94 95

168

40 41

124 125

06K3912.H01723

1/00

Use is further subject to the provisions at the end of this document.

Page 1 of 18

12 3 4 5 6 7...18

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与IBM13N16734JCA-360T相关器件

型号	品牌	获取价格	描述	数据表
IBM13N16734JCA-75AT	IBM	获取价格	Synchronous DRAM Module, 8MX72, 5.4ns, CMOS, DIMM-168
IBM13N2649JC-10	ETC	获取价格	x64 SDRAM Module
IBM13N2649JC-12T	ETC	获取价格	x64 SDRAM Module
IBM13N2739JC-10	ETC	获取价格	x72 SDRAM Module
IBM13N2739JC-10T	IBM	获取价格	Synchronous DRAM Module, 2MX72, 8ns, CMOS, DIMM-168
IBM13N2739JC-12T	ETC	获取价格	x72 SDRAM Module
IBM13N32644JCA-260T	ETC	获取价格	x64 SDRAM Module
IBM13N32644JCA-360T	ETC	获取价格	x64 SDRAM Module
IBM13N32644JCA-75AT	IBM	获取价格	Synchronous DRAM Module, 32MX64, 5.4ns, CMOS, DIMM-168
IBM13N32734JCA-260T	ETC	获取价格	x72 SDRAM Module

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