Datasheet > IBM13N16644HCC-260T

IBM13N16644HCC-260T

更新时间： 2024-10-28 23:57:39

品牌	Logo	应用领域
其他 - ETC		内存集成电路动态存储器时钟
页数	文件大小	规格书
20页	357K
描述
x64 SDRAM Module

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IBM13N16644HCC

IBM13N16734HCC

16M x 64/72 Two-Bank Unbuffered SDRAM Module

Features

• Programmable Operation:

• 168-Pin Unbuffered 8-Byte Dual In-Line Memory

Module

- CAS Latency: 2, 3

• 16Mx64/72 Synchronous DRAM DIMM

• Three speed sorts:

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, 8, Full-Page (Full-

Page supports Sequential burst only)

- Operation: Burst Read and Write or Multiple

Burst Read with Single Write

• -260 and -360 for PC100 applications

• -10 for 66MHz applications (typical)

• Inputs and outputs are LVTTL (3.3V) compatible

• Single 3.3V ± 0.3V Power Supply

• Single Pulsed RAS interface

• Suspend Mode and Power Down Mode

• 12/9/2 Addressing (Row/Column/Bank)

• 4096 Refresh cycles distributed across 64ms

• Serial Presence Detect

• Card size: 5.25" x 1.375" x 0.158" max

• Gold contacts

• SDRAMs in TSOP Type II Package

• SDRAMs have 4 internal banks

• Module has 2 banks

• Fully Synchronous to positive Clock Edge

• Data Mask for Byte Read/Write control

• Auto Refresh (CBR) and Self Refresh

• Automatic and controlled Precharge commands

Description

IBM13N16644HCC / IBM13N16734HCC are unbuf-

fered 168-pin Synchronous DRAM Dual In-Line

Memory Modules (DIMMs) which are organized as

16Mx64 and 16Mx72 high-speed memory arrays.

The DIMMs use sixteen (16Mx64) or eigh-

teen(16Mx72) 8Mx8 SDRAMs in 400mil TSOP II

packages. The DIMMs achieve high-speed data-

transfer rates of up to 100MHz by employing a

prefetch/pipeline hybrid architecture that supports

the JEDEC 1N rule while allowing very low burst

power.

ating modes are defined by combinations of RAS,

CAS, WE, S0-S3, DQMB, and CKE0-CKE1 signals.

A command decoder initiates the necessary timings

for each operation. A 14-bit address bus accepts

address information in a row/column multiplexing

arrangement.

Prior to any Access operation, the CAS latency,

burst type, burst length, and burst operation type

must be programmed into the DIMM by address

inputs A0-A9 during the Mode Register Set cycle.

The DIMM uses serial presence detects imple-

mented via a serial EEPROM using the two pin IIC

protocol. The first 128 bytes of serial PD data are

used by the DIMM manufacturer. The last 128 bytes

are available to the customer.

The -10 speed sort DIMMs comply with JEDEC

standards for 168-pin unbuffered SDRAM DIMMs.

The -260 and -360 speed sort DIMMs are compati-

ble with the Intel PC100 SDRAM unbuffered DIMM

specification.

All IBM 168-pin DIMMs provide a high-performance,

flexible 8-byte interface in a 5.25” long space-saving

footprint. Related products include both EDO DRAM

and SDRAM unbuffered DIMMs in both non-parity

x64 and ECC-Optimized x72 configurations.

All control, address, and data input/output circuits

are synchronized with the positive edge of the exter-

nally supplied clock inputs.

All inputs are sampled at the positive edge of each

externally supplied clock (CK0 - CK3). Internal oper-

Card Outline

(Front)

(Back)

10 11

94 95

40 41

124 125

168

19L7296.E93875B

12/99

Use is further subject to the provisions at the end of this document.

Page 1 of 20

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与IBM13N16644HCC-260T相关器件

型号	品牌	获取价格	描述	数据表
IBM13N16644HCC-360T	ETC	获取价格	x64 SDRAM Module
IBM13N16644JCA-260T	ETC	获取价格	x64 SDRAM Module
IBM13N16644JCA-360T	ETC	获取价格	x64 SDRAM Module
IBM13N16644JCA-75AT	IBM	获取价格	Synchronous DRAM Module, 8MX64, 5.4ns, CMOS, DIMM-168
IBM13N16734HC-360T	IBM	获取价格	Synchronous DRAM Module, 16MX72, 6ns, CMOS, DIMM-168
IBM13N16734HCB-75AT	ETC	获取价格	x72 SDRAM Module
IBM13N16734HCC-10T	ETC	获取价格	x72 SDRAM Module
IBM13N16734HCC-260T	ETC	获取价格	x72 SDRAM Module
IBM13N16734HCC-360T	ETC	获取价格	x72 SDRAM Module
IBM13N16734JCA-260T	ETC	获取价格	x72 SDRAM Module

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