.
IBM13M32734JCA
32M x 72 Two Bank Registered/Buffered SDRAM Module
Features
• 168-Pin Registered 8-Byte Dual In-Line Memory
Module
• 32Mx72 Synchronous DRAM DIMM
• Programmable Operation:
- DIMM CAS Latency: 3, 4 (Registered
mode); 2, 3 (Buffered mode)
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
• Performance:
-260 CL=2 -360 CL=3 -360 CL=2
Units
Reg. Buff. Reg. Buff Reg. Buff.
DIMM CAS Latency
3
2
4
3
3
2
• Data Mask for Byte Read/Write control
• Auto Refresh (CBR) and Self Refresh
• Automatic and controlled Precharge Commands
• Suspend Mode and Power Down Mode
• 12/10/2 Addressing (Row/Column/Bank)
• 4096 refresh cycles distributed across 64ms
• Card size: 5.25" x 0.157" x 1.70"
• Gold contacts
f
f
t
Clock Frequency 100 100 100 100 66
66 MHz
CK
CK
AC
Clock Cycle
10
10
10
10
15
15
ns
Clock Access
7.2 7.2 7.2 7.2 10.2 10.2 ns
• Intended for 66/100MHz & PC100 applications
• Inputs and outputs are LVTTL (3.3V) compatible
• Single 3.3V ± 0.3V Power Supply
• Single Pulsed RAS interface
• SDRAMs have four internal banks
• Module has two physical banks
• SDRAMs in TSOP
• Serial Presence Detect with Write protect
• Fully Synchronous to positive Clock Edge
Description
IBM13M32734JCA is a registered 168-Pin Synchro-
nous DRAM Dual In-Line Memory Module (DIMM)
organized as a 32Mx72 high-speed memory array
and is configured as two 16M x 72 physical banks.
The DIMM uses eighteen 16Mx8 SDRAMs in 400
mil TSOP packages. The DIMM achieves high-
speed data-transfer rates of up to 100 MHz by
employing a prefetch/pipeline hybrid architecture
that synchronizes the output data to a system clock.
(CK0 is connected to the PLL, and CK1, CK2, and
CK3 are terminated on the DIMM.) A single clock
enable (CKE0) controls all devices on the DIMM,
enabling the use of SDRAM power-down modes.
Prior to any access operation, the device CAS
latency and burst type/length/operation type must be
programmed into the DIMM by address inputs A0-A9
and A11 using the mode register set cycle. The
DIMM CAS latency when operated in buffered mode
is the same as the device CAS latency as specified
in the SPD EEPROM. The DIMM CAS latency when
operated in registered mode is one clock later due to
the address and control signals being clocked to the
SDRAM devices.
The DIMM is intended for use in applications operat-
ing from 66MHz to 100 MHz, PC100, memory bus
speeds, and/or heavily loaded bus applications. All
control and address signals are re-driven through
registers/buffers to the SDRAM devices. The DIMM
can be operated in either registered mode (REGE
pin tied high), where the control/address input sig-
nals are latched in the register on one rising clock
edge and sent to the SDRAM devices on the follow-
ing rising clock edge (data access is delayed by one
clock), or in buffered mode (REGE pin tied low)
where the input signals pass through the regis-
ter/buffer to the SDRAM devices on the same clock.
XTK simulation models of the DIMM are available to
determine which mode to design for.
The DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two-pin IIC
protocol. The first 128 bytes of serial PD data are
programmed and locked by the DIMM manufacturer.
The last 128 bytes are available to the customer and
may be write protected by providing a high level to
pin 81 on the DIMM. An on-board pulldown resistor
keeps this in the write-enable mode.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25" long space-saving
footprint.
A phase-lock loop (PLL) on the DIMM is used to re-
drive the clock signals to both the SDRAM devices
and the registers to minimize system clock loading.
09K3883.F38743
4/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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