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IBM04364AQLAD-5 PDF预览

IBM04364AQLAD-5

更新时间: 2024-01-15 19:06:59
品牌 Logo 应用领域
其他 - ETC 静态存储器
页数 文件大小 规格书
24页 297K
描述
x36 Fast Synchronous SRAM

IBM04364AQLAD-5 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:End Of Life零件包装代码:BGA
包装说明:BGA, BGA119,7X17,50针数:119
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
Base Number Matches:1

IBM04364AQLAD-5 数据手册

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.
IBM04184AQLAD  
IBM04364AQLAD  
Preliminary  
128K x 36 & 256K x 18 SRAM  
Features  
• 128K x 36 or 256K x 18 Organizations  
• Common I/O  
CMOS Technology  
• Asynchronous Output Enable and Power Down  
Inputs  
• Synchronous Register Latch Mode Of Operation  
with Self-Timed Late Write  
• Boundary Scan using limited set of JTAG 1149.1  
functions  
• Single Differential Input and Output Clock  
• Byte Write Capability & Global Write Enable  
• +3.3V Power Supply, 1.9V V  
Ground  
, V  
&
REF  
DDQ  
• 7 x 17 Bump Ball Grid Array Package with  
SRAM JEDEC Standard Pinout and Boundary  
SCAN Order  
• Pseudo HSTL Input and Output levels  
• Registered Addresses, Write Enables, Sync  
Select and Data Ins  
• Programmable Impedance Output Drivers  
Description  
The IBM04184AQLAD and IBM04364AQLAD 4Mb  
SRAMS are Synchronous Register Latch Mode, high  
performance CMOS Static Random Access Memo-  
ries that are versatile, wide I/O, and achieve 5.0ns  
access and cycle times. Dual differential K clocks  
are used to initiate the read/write operation, and all  
internal operations are self-timed. At the rising edge  
of the K Clock, all Addresses, Write-Enables, Sync  
Select, and Data Ins are registered internally. An  
internal write buffer allows write data to follow one  
cycle after addresses and controls. The chip is oper-  
ated with a +3.3V core power supply, has a 1.9V or  
1.5V output power supply, and is compatible with  
HSTL I/O interfaces and 1.5V I/O levels as well.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
03K4297.E35614  
Revised 2/99  
Page 1 of 24  

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