Datasheet > IBM04364BSLAD-7(D)

IBM04364BSLAD-7(D)

更新时间： 2024-02-29 04:03:39

品牌	Logo	应用领域
国际商业机器公司 - IBM		静态存储器
页数	文件大小	规格书
21页	464K
描述
Standard SRAM, 128KX36, 3.5ns, CMOS, PBGA119, BGA-119

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技术参数
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IBM04364BSLAD-7(D) 技术参数

生命周期：	Contact Manufacturer	零件包装代码：	BGA
包装说明：	BGA,	针数：	119
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.76
Base Number Matches：	1

IBM04364BSLAD-7(D) 数据手册

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IBM04184BSLAD

IBM04364BSLAD

Preliminary

Features

256K x 18 & 128K x 36 SW SRAM

• 256K x 18 & 128K x 36 Organizations

• CMOS Technology

nous Select and Data Ins

• Registered Outputs

• Synchronous Pipeline Mode Of Operation with

Standard Write

• Asynchronous Output Enable and Power Down

Inputs

• Single Clock compatible with LVTTL Levels

• Boundary Scan using limited set of JTAG 1149.1

functions

• +3.3V Power Supply. Separate Output Power

Supply and Ground

• Byte Write Capability & Global Write Enable

• Common I/O & LVTTL I/O Compatible

• 7 x 17 Bump Ball Grid Array Package with

SRAM JEDEC Standard Pinout and Boundary

• Registered Addresses, Write Enables, Synchro-

Description

IBM0418BSLAD and IBM0436BSLAD (Rev D part

numbers) are 4Mb high performance CMOS Syn-

chronous Static Random Access MemorieS in Pipe-

line Mode that are versatile, wide I/O, and achieve

7ns cycle times. K clock is used to initiate the

read/write operation and all internal operations are

self-timed. At the rising edge of the K Clock, all

Addresses, Write-Enables, Sync Select, and Data

Ins are registered internally. Data Outs are updated

from output registers off the next rising edge of the K

Clock. Data-Ins are registered in the same cycle as

the write controls. The chip is operated with a +3.3V

power supply, optional +2.5V or 3.3V output power

supply, and is compatible with LVTTL I/O interfaces.

Use is further subject to the provisions at the end of this document.

75H4340

Revised 2/99

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