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IBM0436A41NLAB-4 PDF预览

IBM0436A41NLAB-4

更新时间: 2024-09-23 15:45:55
品牌 Logo 应用领域
国际商业机器公司 - IBM 静态存储器
页数 文件大小 规格书
25页 477K
描述
Standard SRAM, 128KX36, 2.25ns, CMOS, PBGA119, BGA-119

IBM0436A41NLAB-4 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:BGA包装说明:BGA, BGA119,7X17,50
针数:119Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.86Is Samacsys:N
Base Number Matches:1

IBM0436A41NLAB-4 数据手册

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IBM0436A41NLAB IBM0418A41NLAB  
IBM0418A81NLAB IBM0436A81NLAB  
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM  
Features  
• 8Mb: 256K x 36 or 512K x 18 organizations  
4Mb: 128K x 36 or 256K x 18 organizations  
• Registered outputs  
• 30 drivers  
• 0.25 Micron CMOS technology  
• Common I/O  
• Synchronous pipeline mode of operation with  
self-timed late write  
• Asynchronous output enable  
• Synchronous power down input  
• Differential PECL clocks or 2.5V LVTTL swing  
with one clock tied to V  
/2  
DDQ  
• Boundary scan using limited set of JTAG 1149.1  
functions  
• +3.3V power supply, ground, 2.5V V  
• 2.5V LVTTL input and output levels  
DDQ  
• Byte write capability and global write enable  
• 7 x 17 bump ball grid array package with SRAM  
JEDEC standard pinout and boundary SCAN  
order  
• Registered addresses, write enables, synchro-  
nous select, and data ins  
Description  
The 4Mb and 8Mb SRAMs—IBM0436A41NLAB,  
IBM0418A41NLAB, IBM0418A81NLAB, and  
IBM0436A81NLAB—are synchronous pipeline  
mode, high-performance CMOS static random-  
access memories that are versatile, have wide I/O,  
and can achieve 3.0ns cycle times. Differential K  
clocks are used to initiate the read/write operation  
and all internal operations are self-timed. At the ris-  
ing edge of the K clock, all addresses, write-  
enables, synchronous select, and data ins are regis-  
tered internally. Data outs are updated from output  
registers on the next rising edge of the K clock. An  
internal write buffer allows write data to follow one  
cycle after addresses and controls. The device is  
operated with a single +3.3V power supply and is  
compatible with a 2.5V LVTTL I/O interface.  
crrL3325.06.fm  
June 13, 2002  
Page 1 of 25  

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