Datasheet > HY67V161610DTC-55

HY67V161610DTC-55

更新时间： 2024-11-07 03:05:31

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
11页	75K
描述
2 Banks x 512K x 16 Bit Synchronous DRAM

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中文翻译

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HY57V161610D

2 Banks x 512K x 16 Bit Synchronous DRAM

DE S CRIPT ION

T H E H y u n d a i H Y 5 7 V 1 6 1 6 1 0 D i s a 1 6 , 7 7 7 , 2 1 6 - b i t s C M O S S y n c h r o n o u s D R A M , i d e a l l y s u i t e d f o r t h e m a i n m e m o r y

and graphic applications which require large memory density and high bandwidth. HY57V161610D is organized as

2banks of 524, 288x16.

HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are

synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-

width. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 1, 2 or 3), the number of consecutive read or

write cycles initiated by

a single control command (Burst length of 1,2,4,8 or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by

design is not restricted by a `2N` rule.)

a new burst read or write command on any cycle. (This pipeline

F EAT URES

Note1)

•

Single 3.0V to 3.6V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

J E D E C s t a n d a r d 4 0 0 m i l 5 0 p i n T S O P - I I w i t h 0 . 8 m m

of pin pitch

P r o g r a m m a b l e B u r s t L e n g t h a n d B u r s t T y p e

- 1, 2, 4, 8 and Full Page for Sequence Burst

- 1, 2, 4 and 8 for Interleave Burst

P r o g r a m m a b l e C A S Latency ; 1, 2, 3 Clocks

•

All inputs and outputs referenced to positive edge of

system clock

•

D a t a m a s k f u n c t i o n b y U D Q M / L D Q M

Internal two banks operation

OR D E R IN G INF ORMAT IO N

Par t No.

C lock Fr equency

O r gani zat i on

I nt erf ace

Package

H Y 5 7 V 1 6 1 6 1 0 D T C - 5

H Y 5 7 V 1 6 1 6 1 0 D T C - 5 5

H Y 5 7 V 1 6 1 6 1 0 D T C - 6

H Y 5 7 V 1 6 1 6 1 0 D T C - 7

H Y 5 7 V 1 6 1 6 1 0 D T C - 8

H Y 5 7 V 1 6 1 6 1 0 D T C - 1 0

2 0 0 M H z

1 8 3 M H z

1 6 6 M H z

1 4 3 M H z

1 2 5 M H z

1 0 0 M H z

400mil

2 B a n k s x 5 1 2 K b i t s x 1 6

L V T T L

5 0 p i n T S O P I I

Note :

1. V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V

This document is

a general product description and is subject to change without notice. Hyundai Electronics does not assume any

responsibility for use of circuits described. No patent licenses are implied

Rev. 3. 6/ Apr . 01

12 3 4 5 6 7...11

中文翻译

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与HY67V161610DTC-55相关器件

型号	品牌	获取价格	描述	数据表
HY67V161610DTC-6	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY67V161610DTC-7	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY67V161610DTC-8	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY67V18100C-12	ETC	获取价格	x18 Fast Synchronous SRAM
HY67V18100C-17	ETC	获取价格	x18 Fast Synchronous SRAM
HY67V18100C-7	ETC	获取价格	x18 Fast Synchronous SRAM
HY67V18101C-12	ETC	获取价格	x18 Fast Synchronous SRAM
HY67V18101C-17	ETC	获取价格	x18 Fast Synchronous SRAM
HY67V18101C-7	ETC	获取价格	x18 Fast Synchronous SRAM
HY67V18110C-20	HYNIX	获取价格	Cache SRAM, 64KX18, 20ns, CMOS, PQCC52, PLASTIC, LCC-52

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