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HY62256ALR1-55 PDF预览

HY62256ALR1-55

更新时间: 2024-11-22 23:57:15
品牌 Logo 应用领域
其他 - ETC 静态存储器
页数 文件大小 规格书
9页 146K
描述
x8 SRAM

HY62256ALR1-55 数据手册

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HY62256A Series  
32Kx8bit CMOS SRAM  
DESCRIPTION  
FEATURES  
The HY62256A is a high-speed, low power and  
32,786 x 8-bits CMOS Static Random Access  
·
·
·
·
Fully static operation and Tri-state output  
TTL compatible inputs and outputs  
Low power consumption  
Battery backup(L/LL-part)  
- 2.0V(min.) data retention  
Standard pin configuration  
- 28 pin 600 mil PDIP  
- 28 pin 330mil SOP  
- 28 pin 8x13.4 mm TSOP-I  
(Standard and Reversed)  
Memory fabricated using  
Hyundai's high  
performance CMOS process technology. The  
HY62256A has a data retention mode that  
guarantees data to remain valid at the minimum  
power supply voltage of 2.0 volt. Using the CMOS  
technology, supply voltages from 2.0 to 5.5volt  
has little effect on supply current in the data  
retention mode. The HY62256A is suitable for use  
in low voltage operation and battery back-up  
application.  
·
Product  
No.  
HY62256A  
Voltage  
(V)  
Speed  
(ns)  
55/70/85  
Operation  
Current(mA)  
50  
Standby Current(uA)  
Temperature  
(°C)  
0~70(Normal)  
L
100  
LL  
25  
5.0  
1mA  
Note 1. Current value is max.  
PIN CONNECTION  
Vcc  
A14  
A12  
A7  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
A14  
A12  
A7  
Vcc  
/WE  
A13  
A8  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
/WE  
A13  
A8  
/OE  
A11  
A9  
A10  
/CS  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
Vss  
I/O3  
I/O2  
I/O1  
A0  
A3  
A4  
A2  
3
1
2
28  
14  
13  
12  
11  
10  
9
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
3
A1  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
A6  
4
A6  
4
A5  
A0  
3
A9  
A5  
5
A5  
A9  
5
A8  
A6  
I/O1  
I/O2  
I/O3  
Vss  
I/O4  
I/O5  
I/O6  
I/O7  
I/O8  
/CS  
A10  
4
A4  
A11  
/OE  
A10  
/CS  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
6
A11  
/OE  
A10  
/CS  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
A4  
6
A13  
/WE  
Vcc  
A14  
A12  
A7  
A7  
5
A3  
7
A3  
7
A12  
A14  
Vcc  
/WE  
A13  
A8  
6
A2  
8
A2  
7
8
8
A1  
8
7
A1  
9
9
9
6
A0  
10  
11  
12  
13  
14  
A0  
10  
11  
12  
13  
14  
10  
11  
12  
13  
14  
5
I/O1  
I/O2  
I/O3  
Vss  
I/O1  
I/O2  
I/O3  
Vss  
A6  
4
A5  
A9  
A11  
/OE  
3
A4  
A1  
2
1
A3  
A2  
PDIP  
SOP  
TSOP-I(Standard)  
TSOP-I(Reversed)  
PIN DESCRIPTION  
BLOCK DIAGRAM  
ROW DECODER  
I/O1  
A0  
Pin Name  
Pin Function  
Chip Select  
Write Enable  
/CS  
/WE  
MEMORY ARRAY  
512x512  
/OE  
Output Enable  
Address Inputs  
Data Input/Output  
Power(+5.0V)  
Ground  
A0 ~ A14  
I/O1 ~ I/O8  
Vcc  
A14  
I/O8  
/CS  
Vss  
/OE  
/WE  
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev.02 /Jun.99  
Hyundai Semiconductor  

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