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HY5W2A2F-PC PDF预览

HY5W2A2F-PC

更新时间: 2024-02-28 18:35:18
品牌 Logo 应用领域
海力士 - HYNIX 时钟动态存储器内存集成电路
页数 文件大小 规格书
25页 372K
描述
Synchronous DRAM, 4MX32, 7ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90

HY5W2A2F-PC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:TFBGA, BGA90,9X15,32针数:90
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.84
访问模式:FOUR BANK PAGE BURST最长访问时间:7 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:R-PBGA-B90JESD-609代码:e1
长度:13 mm内存密度:134217728 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:32
功能数量:1端口数量:1
端子数量:90字数:4194304 words
字数代码:4000000工作模式:SYNCHRONOUS
最高工作温度:80 °C最低工作温度:-10 °C
组织:4MX32输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA90,9X15,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:1.8/2.5,2.5 V认证状态:Not Qualified
刷新周期:4096座面最大高度:1.2 mm
自我刷新:YES连续突发长度:1,2,4,8,FP
最大待机电流:0.0006 A子类别:DRAMs
最大压摆率:0.13 mA最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:8 mmBase Number Matches:1

HY5W2A2F-PC 数据手册

 浏览型号HY5W2A2F-PC的Datasheet PDF文件第6页浏览型号HY5W2A2F-PC的Datasheet PDF文件第7页浏览型号HY5W2A2F-PC的Datasheet PDF文件第8页浏览型号HY5W2A2F-PC的Datasheet PDF文件第10页浏览型号HY5W2A2F-PC的Datasheet PDF文件第11页浏览型号HY5W2A2F-PC的Datasheet PDF文件第12页 
HY5W2A2(L/S)F-C / HY57W2A3220(L/S)T-C  
HY5W22F-C / HY57W283220T-C  
4Banks x 1M x 32bits Synchronous DRAM  
COMMAND TRUTH TABLE  
A10/  
AP  
Function  
CKEn-1  
CKEn  
CS  
RAS CAS WE DQM ADDR  
BA Note  
Mode Register Set  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
Op Code  
2
2
Extended Mode Register Set  
L
L
L
Op Code  
No Operation  
H
X
L
H
X
H
L
H
X
H
H
H
L
X
X
Device Deselect  
Bank Active  
Read  
Row Address  
V
V
V
V
V
X
V
Column  
L
H
H
H
H
L
Read with Autoprecharge  
Write  
L
X
X
X
X
X
X
X
V
X
X
X
Column  
Column  
Column  
X
H
L
L
Write with Autoprecharge  
L
L
H
H
L
Precharge All Banks  
H
H
H
L
Precharge selected Bank  
L
L
X
Burst stop  
H
L
X
X
X
X
X
X
Data Write/Output Enable  
Data Mask/Output Disable  
Auto Refresh  
X
X
L
L
L
H
H
X
H
X
H
X
H
X
V
Self Refresh Entry  
Self Refresh Exit  
L
L
L
H
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
1
Precharge Power Down  
Entry  
H
L
L
H
L
X
X
X
X
X
X
Precharge Power Down Exit  
Clock Suspend Entry  
Clock Suspend Exit  
H
L
H
L
H
H
L
L
H
L
H
L
X
X
X
X
X
X
X
X
Deep Power Down Entry  
Deep Power Down Exit  
L
H
H
L
H
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.  
2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set.  
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume  
any responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.5/Nov. 02  

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