Datasheet > HY5W2A2F-PC

HY5W2A2F-PC

更新时间： 2024-02-04 20:51:47

品牌	Logo	应用领域
海力士 - HYNIX		时钟动态存储器内存集成电路
页数	文件大小	规格书
25页	372K
描述
Synchronous DRAM, 4MX32, 7ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90

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技术参数
数据手册

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HY5W2A2F-PC 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	TFBGA, BGA90,9X15,32	针数：	90
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.02	风险等级：	5.84
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	7 ns
其他特性：	AUTO/SELF REFRESH	最大时钟频率 (fCLK)：	100 MHz
I/O 类型：	COMMON	交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PBGA-B90	JESD-609代码：	e1
长度：	13 mm	内存密度：	134217728 bit
内存集成电路类型：	SYNCHRONOUS DRAM	内存宽度：	32
功能数量：	1	端口数量：	1
端子数量：	90	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	80 °C	最低工作温度：	-10 °C
组织：	4MX32	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFBGA
封装等效代码：	BGA90,9X15,32	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	1.8/2.5,2.5 V	认证状态：	Not Qualified
刷新周期：	4096	座面最大高度：	1.2 mm
自我刷新：	YES	连续突发长度：	1,2,4,8,FP
最大待机电流：	0.0006 A	子类别：	DRAMs
最大压摆率：	0.13 mA	最大供电电压 (Vsup)：	2.7 V
最小供电电压 (Vsup)：	2.3 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL EXTENDED	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	20
宽度：	8 mm	Base Number Matches：	1

HY5W2A2F-PC 数据手册

HY5W2A2(L/S)F-C / HY57W2A3220(L/S)T-C

HY5W22F-C / HY57W283220T-C

4Banks x 1M x 32bits Synchronous DRAM

Power Up and Initialization

Like a Synchronous DRAM, Low Power SDRAM must be powered up and initialized in a predefined manner. Power must be applied to

VDD and VDDQ(simultaneously). The clock signal must be started at the same time. After power up, an initial pause of 200 µsec is re-

quired. And a precharge all command will be issued to the LP SDRAM. Then, 8 or more Auto refresh cycles will be provided. After the

Auto refresh cycles are completed, a mode register set(MRS) command will be issued to program the specific mode of operation (Cas

Latency, Burst length, etc.) And a extended mode register set command will be issued to program specific mode of self refresh opera-

tion(PASR & TCSR). The following these cycles, the LP SDRAM is ready for normal opeartion.

Programming the registers

Mode Register

The mode register contains the specific mode of operation of the LP SDRAM. This register includes the selection of a burst length(1, 2, 4,

8, Full Page), a cas latency(1, 2, or 3), a burst type, an opearting mode to differentiate between normal mode and a special burst read and

single write mode. The mode register set must be done before any activate command after the power up sequence. Any contents of the

mode register be altered by re-programming the mode register through the execution of mode register set command.

Extended Mode Register

The extended mode register contains the specific features of self refresh opeartion of the LP SDRAM. This register includes the selection

of partial arrays to be refreshed(half array, quarter array, etc.), tempearture range of the device(85, 70, 45, 15) for reducing current con-

sumption during self refresh. The extended mode register set must be done before any activate command after the power up sequence.

Any contents of the mode register be altered by re-programming the mode register through the execution of extended mode register set

command.

Bank(Row) Active

The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating CS, RAS

and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects the bank, and the value on the A0-A11

selects the row. This row remains active for column access until a precharge command is issued to that bank. Read and write opeartions

can only be initiated on this activated bank after the minimum tRCD time is passed from the activate command.

Read

The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deasserting WE, RAS

at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the sarting column location. The value

on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged

at the end of the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses.The length of burst and

the CAS latency will be determined by the values programmed during the MRS command.

Write

The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and deasserting RAS

at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the starting column location. The value

on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged

at the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses.

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume

any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.5/Nov. 02

1...4 5 678 9 10...25

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与HY5W2A2F-PC相关器件

型号	品牌	描述	获取价格	数据表
HY5W2A2LF-8	HYNIX	Synchronous DRAM, 4MX32, 6ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90	获取价格
HY5W2A2LF-HC	HYNIX	Synchronous DRAM, 4MX32, 5.4ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90	获取价格
HY5W2A2LF-PC	HYNIX	Synchronous DRAM, 4MX32, 7ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90	获取价格
HY5W2A2SF-P	HYNIX	Synchronous DRAM, 4MX32, 7ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90	获取价格
HY5W2A6CF-H	HYNIX	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54	获取价格
HY5W2A6CF-P	HYNIX	Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54	获取价格

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