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HY57V641620HGT-6I PDF预览

HY57V641620HGT-6I

更新时间： 2024-11-28 22:23:27
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器
页数 文件大小 规格书
12页 146K
描述
4 Banks x 1M x 16Bit Synchronous DRAM

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中文翻译

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HY57V641620HGT-6I 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSOP2包装说明：TSOP2, TSOP54,.46,32
针数：54Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.02
风险等级：5.88访问模式：FOUR BANK PAGE BURST
最长访问时间：5.4 ns其他特性：AUTO/SELF REFRESH
最大时钟频率 (fCLK)：166 MHzI/O 类型：COMMON
交错的突发长度：1,2,4,8JESD-30 代码：R-PDSO-G54
长度：22.238 mm内存密度：67108864 bit
内存集成电路类型：SYNCHRONOUS DRAM内存宽度：16
功能数量：1端口数量：1
端子数量：54字数：4194304 words
字数代码：4000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：4MX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装等效代码：TSOP54,.46,32封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
刷新周期：4096座面最大高度：1.194 mm
自我刷新：YES连续突发长度：1,2,4,8,FP
最大待机电流：0.002 A子类别：DRAMs
最大压摆率：0.16 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10.16 mm
Base Number Matches：1

HY57V641620HGT-6I 数据手册

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HY57V641620HG-I Series  
4 Banks x 1M x 16Bit Synchronous DRAM  
DESCRIPTION  
The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications r which require  
low power consumption and extended temperature range. HY57V641620HG is organized as 4banks of 1,048,576x16.  
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-  
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output  
voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated  
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of  
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst  
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)  
FEATURES  
Single 3.3±0.3V power supply Note)  
•
•
•
Auto refresh and self refresh  
•
•
•
4096 refresh cycles / 64ms  
All device pins are compatible with LVTTL interface  
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 or Full page for Sequential Burst  
- 1, 2, 4 or 8 for Interleave Burst  
JEDEC standard 400mil 54pin TSOP-II with 0.8mm  
of pin pitch  
•
All inputs and outputs referenced to positive edge of  
system clock  
•
Programmable CAS Latency ; 2, 3 Clocks  
•
•
Data mask function by UDQM or LDQM  
Internal four banks operation  
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Power  
Organization  
Interface  
Package  
HY57V641620HGT-5I/55I/6I/7I  
HY57V641620HGT-KI  
HY57V641620HGT-HI  
HY57V641620HGT-8I  
200/183/166/143MHz  
133MHz  
133MHz  
Normal  
125MHz  
HY57V641620HGT-PI  
HY57V641620HGT-SI  
HY57V641620HGLT-5I/55I/6I/7I  
HY57V641620HGLT-KI  
HY57V641620HGLT-HI  
HY57V641620HGLT-8I  
HY57V641620HGLT-PI  
HY57V641620HGLT-SI  
100MHz  
100MHz  
4Banks x 1Mbits  
x16  
LVTTL  
400mil 54pin TSOP II  
200/183/166/143MHz  
133MHz  
133MHz  
Low power  
125MHz  
100MHz  
100MHz  
Note : VDD(Min) of HY57V641620HG(L)T-5I/55I/6I is 3.135V  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use  
of circuits described. No patent licenses are implied.  
Rev. 1.0/Jan. 02  
1
1234567...12

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