Datasheet > HY57V283220T-SI

HY57V283220T-SI

更新时间： 2024-11-08 10:55:03

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器光电二极管
页数	文件大小	规格书
14页	292K
描述
Synchronous DRAM, 4MX32, 6ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86

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数据手册

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HY57V283220T-SI 数据手册

HY57V283220T-I / HY5V22F-I

PIN CONFIGURATION ( HY57V283220T-I Series)

V D D

D Q 0

V D D Q

D Q 1

D Q 2

V S S Q

D Q 3

D Q 4

8 6

8 5

8 4

8 3

8 2

8 1

8 0

7 9

7 8

7 7

7 6

7 5

7 4

7 3

7 2

7 1

7 0

6 9

6 8

6 7

6 6

6 5

6 4

6 3

6 2

6 1

6 0

5 9

5 8

5 7

5 6

5 5

5 4

5 3

5 2

5 1

5 0

4 9

4 8

4 7

4 6

4 5

4 4

V S S

D Q 1 5

V S S Q

D Q 1 4

D Q 1 3

V D D Q

D Q 1 2

D Q 1 1

V S S Q

D Q 1 0

D Q 9

V D D Q

D Q 8

N C

D D Q

D Q 5

D Q 6

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

2 5

2 6

2 7

2 8

2 9

3 0

3 1

3 2

3 3

3 4

3 5

3 6

3 7

3 8

3 9

4 0

4 1

4 2

4 3

V S S Q

D Q 7

N C

V D D

V S S

D Q M 0

/W E

D Q M 1

N C

/C A S

/R A S

/C S

N C

C L K

C K E

A 9

8 6 p in T S O P II

4 0 0 m il x 8 7 5 m il

0 .5 m m p in p itc h

A 1 1

B A 0

B A 1

A 1 0 /A P

A 0

A 8

A 7

A 6

A 5

A 1

A 4

A 2

A 3

D Q M 2

V D D

D Q M 3

V S S

N C

D Q 1 6

D Q 3 1

V D D Q

D Q 3 0

D Q 2 9

V S S Q

D Q 2 8

D Q 2 7

V D D Q

D Q 2 6

D Q 2 5

V S S Q

D Q 2 4

V S S

S S Q

D Q 1 7

D Q 1 8

D D Q

D Q 1 9

D Q 2 0

V S S Q

D Q 2 1

D Q 2 2

V D D Q

D Q 2 3

V D D

PIN DESCRIPTION

PIN NAME

DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK.

CLK

Clock

Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh

CKE

Clock Enable

Chip Select

Enables or disables all inputs except CLK, CKE and DQM

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

BA0, BA1

Bank Address

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7

Auto-precharge flag : A10

A0 ~ A11

Address

Row Address Strobe,

Column Address Strobe,

Write Enable

RAS, CAS and WE define the operation

Refer function truth table for details

RAS, CAS, WE

DQM0~3

DQ0 ~ DQ31

VDD/VSS

VDDQ/VSSQ

Data Input/Output Mask

Data Input/Output

Controls output buffers in read mode and masks input data in write mode

Multiplexed data input / output pin

Power Supply/Ground

Power supply for internal circuits and input buffers

Power supply for output buffers

Data Output Power/Ground

No Connection

No connection

Rev. 0.6/Nov. 02

123 4 5 6 7...14

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HY57V28420ALT-6	ETC	获取价格	x4 SDRAM
HY57V28420ALT-8	ETC	获取价格	x4 SDRAM
HY57V28420ALT-H	ETC	获取价格	x4 SDRAM
HY57V28420ALT-K	ETC	获取价格	x4 SDRAM
HY57V28420ALT-P	ETC	获取价格	x4 SDRAM
HY57V28420ALT-S	ETC	获取价格	x4 SDRAM
HY57V28420AT	ETC	获取价格	32Mx4\|3.3V\|4K\|6/K/H/8/P/S\|SDR SDRAM - 128M
HY57V28420AT-10	ETC	获取价格	x4 SDRAM