Datasheet > HY57V283220(L)T(P)-8

HY57V283220(L)T(P)-8

更新时间： 2022-11-24 21:47:20

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
15页	914K
描述
4 Banks x 1M x 32Bit Synchronous DRAM

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HY57V283220(L)T(P)-8 数据手册

HY57V283220(L)T(P)/ HY5V22(L)F(P)

4 Banks x 1M x 32Bit Synchronous DRAM

Revision History

Revision No.

History

Remark

0.1

0.2

Defined Preliminary Specification

1) Modified FBGA Ball Configuration Typo.

2) Changed Functional Block Diagram from A10 to A11.

3) Changed VDD min from 3.0V to 3.135V.

4) Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf.

5) Insert tAC2 Value.

6) Insdrt tRAS & CLK Value.

0.3

0.4

0.5

0.6

0.7

Defined IDD Spec.

Delited Preliminary.

Changed IDD Spec.

133MHz Speed Added

Changed FBGA Package Size from 11x13 to 8x13.

1) Changed VDD min from 3.135V to 3.0V.

2) Changed VIL min from VSSQ-0.3V to -0.3V.

0.8

0.9

Modified of size erra. (Page15)

(Equation : 13.00 ± 10 -> 13.00 ± 0.10)

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume

any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.9 / July 2004

12 3 4 5 6 7...15

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型号	品牌	获取价格	描述	数据表
HY57V283220(L)T(P)-H	HYNIX	获取价格	4 Banks x 1M x 32Bit Synchronous DRAM
HY57V283220(L)T(P)-P	HYNIX	获取价格	4 Banks x 1M x 32Bit Synchronous DRAM
HY57V283220(L)T(P)-S	HYNIX	获取价格	4 Banks x 1M x 32Bit Synchronous DRAM
HY57V283220LT	ETC	获取价格	4Mx32\|3.3V\|4K\|55/6/7/8/P/S\|SDR SDRAM - 128M
HY57V283220LT-5	HYNIX	获取价格	4 Banks x 1M x 32Bit Synchronous DRAM
HY57V283220LT-55	HYNIX	获取价格	4 Banks x 1M x 32Bit Synchronous DRAM
HY57V283220LT-55I	HYNIX	获取价格	Synchronous DRAM, 4MX32, 5ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86
HY57V283220LT-6	HYNIX	获取价格	4 Banks x 1M x 32Bit Synchronous DRAM
HY57V283220LT-6I	HYNIX	获取价格	暂无描述
HY57V283220LT-7	HYNIX	获取价格	4 Banks x 1M x 32Bit Synchronous DRAM