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HV574PG-G PDF预览

HV574PG-G

更新时间: 2024-11-07 01:23:39
品牌 Logo 应用领域
超科 - SUPERTEX /
页数 文件大小 规格书
7页 633K
描述
100MHz, 80-Channel Serial to Parallel Converter with Push-Pull Outputs

HV574PG-G 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFP包装说明:,
针数:100Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.82接口集成电路类型:BUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 代码:R-PQFP-G100JESD-609代码:e3
端子数量:100输出电流流向:SOURCE AND SINK
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified表面贴装:YES
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED

HV574PG-G 数据手册

 浏览型号HV574PG-G的Datasheet PDF文件第2页浏览型号HV574PG-G的Datasheet PDF文件第3页浏览型号HV574PG-G的Datasheet PDF文件第4页浏览型号HV574PG-G的Datasheet PDF文件第5页浏览型号HV574PG-G的Datasheet PDF文件第6页浏览型号HV574PG-G的Datasheet PDF文件第7页 
Supertex inc.  
HV574  
100MHz, 80-Channel Serial to Parallel Converter  
with Push-Pull Outputs  
Features  
General Description  
HVCMOS® technology  
5.0V CMS Logic  
The HV574 is a low-voltage serial to high-voltage parallel con-verter  
with push-pull outputs. This device has been designed for use as a  
driver for printer applications. It can also be used in any application  
requiring multiple output high-voltage current sour-cing and sinking  
capability such as driving plasma panels, vacuum fluorescent  
displays, or large matrix LCD displays.  
Output voltage up to 80V  
Low power level shifting  
100MHz equivalent data rate using four  
dynamic shift registers  
Latched data outputs  
The device has 4 parallel 20-bit dynamic shift registers, permitting  
data rates 4X the speed of one (they are clocked together). There  
are 80 static latches and control logic to perform the polarity select  
and blanking of the outputs. HVOUT1 is connected to the first stage of  
the first shift register through the polarity and blanking logic. Data is  
shifted through the shift registers on the logic low to high transition  
of the clock. The DIR pin causes CCW shifting when connected to  
GND, and CW shifting when connected to VDD. A data output buffer  
is provided for cascading devices. This output reflects the current  
status of the last bit of the shift register (HVOUT80). Operation of the  
shift register is not affected by the LE (latch enable), BL (blanking),  
or the POL (polarity) inputs. Transfer of data from the shift registers  
to the latches occurs when the LE (latch enable) input is high. The  
data in the latches is stored when LE is low.  
Foreward and reverse shifting options (DIR pin)  
Diode to VPP allows efficient power recovery  
Outputs may be hot switched  
Functional Block Diagram  
VDD  
POL  
VPP  
LE  
BL  
HVOUT  
1
DIR  
20-bit  
DINA  
Shift  
D
OUTA  
Register  
HVOUT20  
HVOUT21  
HVOUT40  
HVOUT41  
HVOUT60  
HVOUT61  
HVOUT80  
CLK  
20-bit  
Shift  
D B  
DOUINTB  
Register  
20-bit  
Shift  
Register  
DINC  
D
OUTC  
20-bit  
Shift  
Register  
DIND  
OUTD  
D
GND  
Doc.# DSFP-HV574  
A061913  
Supertex inc.  
www.supertex.com  

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