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HM5212165FTD-75A PDF预览

HM5212165FTD-75A

更新时间: 2024-10-27 19:34:23
品牌 Logo 应用领域
日立 - HITACHI 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
53页 2022K
描述
Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

HM5212165FTD-75A 数据手册

 浏览型号HM5212165FTD-75A的Datasheet PDF文件第2页浏览型号HM5212165FTD-75A的Datasheet PDF文件第3页浏览型号HM5212165FTD-75A的Datasheet PDF文件第4页浏览型号HM5212165FTD-75A的Datasheet PDF文件第5页浏览型号HM5212165FTD-75A的Datasheet PDF文件第6页浏览型号HM5212165FTD-75A的Datasheet PDF文件第7页 
HM5212165F-75A  
HM5212805F-75A  
128M LVTTL interface SDRAM  
133 MHz  
2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank  
PC/133 SDRAM  
ADE-203-1049 (Z)  
Preliminary  
Rev. 0.0  
May. 20, 1999  
Description  
The Hitachi HM5212165F is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The Hita-  
chi HM5212805F is a 128-Mbit SDRAM organized as 4194304-word × 8-bit × 4-bank. All inputs and out-  
puts are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.  
Features  
3.3 V power supply  
Clock frequency: 133 MHz (max)  
LVTTL interface  
Single pulsed RAS  
4 banks can operate simultaneously and independently  
Burst read/write operation and burst read/single write operation capability  
Programmable burst length: 1/2/4/8/full page  
2 variations of burst sequence  
— Sequential (BL = 1/2/4/8/full page)  
— Interleave (BL = 1/2/4/8)  
Programmable CAS latency: 2/3  
Byte control by DQM : DQM (HM5212805F)  
: DQMU/DQML (HM5212165F)  
Refresh cycles: 4096 refresh cycles/64 ms  
2 variations of refresh  
— Auto refresh  
— Self refresh  
Full page burst length capability  
— Sequential burst  
— Burst stop capability  

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