Datasheet > HDMP-0452

HDMP-0452

更新时间： 2024-02-29 20:14:37

品牌	Logo	应用领域
安捷伦 - AGILENT		光纤
页数	文件大小	规格书
12页	275K
描述
Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops

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技术参数
数据手册

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HDMP-0452 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP,	针数：	44
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	S-PQFP-G44
长度：	10 mm	功能数量：	1
端子数量：	44	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装形状：	SQUARE
封装形式：	FLATPACK	认证状态：	Not Qualified
座面最大高度：	2.45 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
宽度：	10 mm	Base Number Matches：	1

HDMP-0452 数据手册

Agilent HDMP-0452

Quad Port Bypass Circuit

with CDR for Fibre Channel

Arbitrated Loops

Data Sheet

Features

• Supports 1.0625 GBd fibre

channel operation

• Supports 1.25 GBd Gigabit

Ethernet (GE) operation

Description

Transceiver IC’s Tx± differential

outputs goes to the HDMP-0452’s

FM_NODE[n]± differential input

pins. Figures 3 and 4 show con-

nection diagrams for disk drive

array applications. When the “disk

bypassed” mode is selected, the

disk drive is either absent or non-

functional and the loop bypasses

the hard disk.

• Quad PBC/CDR in one package

• CDR location determined by

choice of cable input/output

• Valid amplitude detection on

FM_NODE[0] input

• Equalizers on all inputs

• High speed LVPECL I/O

The HDMP-0452 is a Quad Port

Bypass Circuit (PBC) with a Clock

and Data Recovery (CDR) circuit

included. This device minimizes

part count, cost and jitter accumula-

tion while repeating incoming sig-

nals. Port Bypass Circuits are used

in hard disk arrays constructed in

Fibre Channel Arbitrated Loop

(FC-AL) configurations. By using

Port Bypass Circuits, hard disks

may be pulled out or swapped while

other disks in the array are available

to the system.

• Buffered Line Logic (BLL) outputs

(no external bias resistors

required)

The “disk bypassed” mode is

enabled by pulling the

• 0.66 W typical power at

= 3.3 V

BYPASS[n]– pin low. Leave

BYPASS[n]– floating to enable

the “disk in loop” mode. HDMP-

0452s may be cascaded with other

members of the HDMP-04XX/

HDMP-05XX family through the

FM_LOOP and TO_LOOP pins to

accommodate any number of hard

disks. See Table 2 to identify

which of the 5 cells (0:4) will

provide FM_LOOP and TO_LOOP

pins (cable connections). The

unused cells in this PBC may be

bypassed by using pulldown

resistors on the BYPASS[n]– pins

for these cells.

• 44 pin, 10 mm, low cost plastic

QFP package

A Port Bypass Circuit (PBC) con-

sists of multiple 2:1 multiplexers

daisy chained along with a CDR.

Each port has two modes of opera-

tion: “disk in loop” and “disk by-

passed”. When the “disk in loop”

mode is selected, the loop goes into

and out of the disk drive at that

port. For example, data goes from

the HDMP-0452’s TO_NODE[n]±

differential output pins to the Disk

Drive Transceiver IC’s (e.g., an

HDMP-1536A) Rx± differential

input pins. Data from the Disk Drive

Applications

• RAID, JBOD, BTS cabinets

• 1 => 1-4 serial buffer with or

w/o CDR

HDMP-0452

CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assem-

bly of this component to prevent damage and/or degradation which may be induced by Electrostatic Discharge (ESD).

12 3 4 5 6 7...12

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与HDMP-0452相关器件

型号	品牌	获取价格	描述	数据表
HDMP-0480	AGILENT	获取价格	Octal Cell Port Bypass Circuit without Clock and Data Recovery
HDMP-0482	AGILENT	获取价格	Octal Cell Port Bypass Circuit with CDR and Data Valid Detection
HDMP-0482	HP	获取价格	Octal Cell Port Bypass Circuit with CDR and Data Valid Detection
HDMP-0482G	PMC	获取价格	ATM/SONET/SDH Clock Recovery Circuit, PQFP64,
HDMP-0552	ETC	获取价格	AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA VALID DETECTION
HDMP1000	ETC	获取价格	Optoelectronic
HDMP-1000	AGILENT	获取价格	Telecom Circuit, 1-Func, Bipolar, CQFP68, CERAMIC, QFP-68
HDMP-1002	ETC	获取价格	Receiver
HDMP-1004	ETC	获取价格	Transmitter
HDMP-1012	AGILENT	获取价格	4Low Cost Gigabit Rate Transmit/Receive Chip Set

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