Agilent HDMP-0482
Octal Cell Port Bypass Circuit
with CDR and Data Valid Detection
Data Sheet
Features
• Supports 1.0625 GBd fibre channel
operation
• Supports 1.25 GBd Gigabit Ethernet
(GE) operation
•
Octal cell PBC/CDR in one package
• CDR location determined by choice
of cable input/output
Description
the HDMP-0482’s FM_NODE[n]
differential input pins. When the
“disk bypassed” mode is selected,
the disk drive is either absent or
non-functional and the loop
bypasses the hard disk.
• Amplitude valid detection on
FM_NODE[7] input
The HDMP-0482 is an Octal Cell
Port Bypass Circuit (PBC) with
Clock and Data Recovery (CDR)
and data valid detection capabil-
ity included. This device mini-
mizes part count, cost and jitter
accumulation while repeating
incoming signals. Port Bypass
Circuits are used in hard disk
arrays constructed in Fibre
Channel Arbitrated Loop
(FC-AL) configurations. By using
Port Bypass Circuits, hard disks
may be pulled out or swapped
while other disks in the array are TO_NODE pins to accommodate
available to the system.
• Data valid detection on
FM_NODE[0] input
– Run length violation detection
– Comma detection
The “disk bypassed” mode is
enabled by pulling the BYPASS[n]-
pin low. Leave BYPASS[n]-
floating to enable the “disk in
loop” mode. HDMP-0482’s may be
cascaded with other members of
the HDMP-04XX/HDMP-05XX
family through the FM_NODE and
– Configurable for both single-
frame and multi-frame detection
• Equalizers on all inputs
• High speed LVPECL I/O
• Buffered Line Logic (BLL) outputs
(no external bias resistors
required)
• 1.09 W typical power at Vcc=3.3V
any number of hard disks. The
unused cells in this PBC may be
bypassed by using pulldown
• 64 Pin, 14 mm, low cost plastic QFP
package
A Port Bypass Circuit (PBC)
consists of multiple 2:1 multiplex- resistors on the BYPASS[n]- pins
Applications
• RAID, JBOD, BTS cabinets
ers daisy chained along with a
CDR. Each port has two modes of
operation: “disk in loop” and
“disk bypassed”. When the “disk
for these cells.
• Four 2:1 muxes
An HDMP-0482 may also be used
as eight 1:1 buffers, one with a
• Four 1:2 buffers
in loop” mode is selected, the loop CDR and seven without. For
goes into and out of the disk drive example, an HDMP-0482 may be
• 1 = > N gigabit serial buffer
• N = > 1 gigabit serial mux
at that port. For example, data
goes from the HDMP-0482’s
placed in front of a CMOS ASIC
to clean the jitter of the outgoing
signal (CDR path) and to better
TO_NODE[n] differential output
pins to the Disk Drive Transceiver read the incoming signal (non-
IC’s (e.g. an HDMP-1636A) Rx
differential input pins. Data from
the Disk Drive Transceiver IC’s
Tx differential outputs goes to
CDR path). In addition, the
HDMP-0482 may be configured as
four 2:1 multiplexers or as four
1:2 buffers.
HDMP-0482
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions
be taken in the handling and assembly of this component to prevent damage and/or
degradation which may be induced by electrostatic discharge (ESD).