HDMP-0482

更新时间： 2024-10-04 03:41:27

品牌	Logo	应用领域
安捷伦 - AGILENT		电信集成电路电信电路异步传输模式 ATM
页数	文件大小	规格书
12页	146K
描述
Octal Cell Port Bypass Circuit with CDR and Data Valid Detection

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

HDMP-0482 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	QFP, QFP64,.51SQ,20
针数：	64	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.89
Is Samacsys：	N	JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e0	长度：	14 mm
功能数量：	1	端子数量：	64
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP64,.51SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	2.35 mm	子类别：	ATM/SONET/SDH ICs
最大压摆率：	0.4 mA	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

HDMP-0482 数据手册

Agilent HDMP-0482

Octal Cell Port Bypass Circuit

with CDR and Data Valid Detection

Data Sheet

Features

• Supports 1.0625 GBd fibre channel

operation

• Supports 1.25 GBd Gigabit Ethernet

(GE) operation

•

Octal cell PBC/CDR in one package

• CDR location determined by choice

of cable input/output

Description

the HDMP-0482’s FM_NODE[n]

differential input pins. When the

“disk bypassed” mode is selected,

the disk drive is either absent or

non-functional and the loop

bypasses the hard disk.

• Amplitude valid detection on

FM_NODE[7] input

The HDMP-0482 is an Octal Cell

Port Bypass Circuit (PBC) with

Clock and Data Recovery (CDR)

and data valid detection capabil-

ity included. This device mini-

mizes part count, cost and jitter

accumulation while repeating

incoming signals. Port Bypass

Circuits are used in hard disk

arrays constructed in Fibre

Channel Arbitrated Loop

(FC-AL) configurations. By using

Port Bypass Circuits, hard disks

may be pulled out or swapped

while other disks in the array are TO_NODE pins to accommodate

available to the system.

• Data valid detection on

FM_NODE[0] input

– Run length violation detection

– Comma detection

The “disk bypassed” mode is

enabled by pulling the BYPASS[n]-

pin low. Leave BYPASS[n]-

floating to enable the “disk in

loop” mode. HDMP-0482’s may be

cascaded with other members of

the HDMP-04XX/HDMP-05XX

family through the FM_NODE and

– Configurable for both single-

frame and multi-frame detection

• Equalizers on all inputs

• High speed LVPECL I/O

• Buffered Line Logic (BLL) outputs

(no external bias resistors

required)

• 1.09 W typical power at Vcc=3.3V

any number of hard disks. The

unused cells in this PBC may be

bypassed by using pulldown

• 64 Pin, 14 mm, low cost plastic QFP

package

A Port Bypass Circuit (PBC)

consists of multiple 2:1 multiplex- resistors on the BYPASS[n]- pins

Applications

• RAID, JBOD, BTS cabinets

ers daisy chained along with a

CDR. Each port has two modes of

operation: “disk in loop” and

“disk bypassed”. When the “disk

for these cells.

• Four 2:1 muxes

An HDMP-0482 may also be used

as eight 1:1 buffers, one with a

• Four 1:2 buffers

in loop” mode is selected, the loop CDR and seven without. For

goes into and out of the disk drive example, an HDMP-0482 may be

• 1 = > N gigabit serial buffer

• N = > 1 gigabit serial mux

at that port. For example, data

goes from the HDMP-0482’s

placed in front of a CMOS ASIC

to clean the jitter of the outgoing

signal (CDR path) and to better

TO_NODE[n] differential output

pins to the Disk Drive Transceiver read the incoming signal (non-

IC’s (e.g. an HDMP-1636A) Rx

differential input pins. Data from

the Disk Drive Transceiver IC’s

Tx differential outputs goes to

CDR path). In addition, the

HDMP-0482 may be configured as

four 2:1 multiplexers or as four

1:2 buffers.

HDMP-0482

CAUTION: As with all semiconductor ICs, it is advised that normal static precautions

be taken in the handling and assembly of this component to prevent damage and/or

degradation which may be induced by electrostatic discharge (ESD).

12 3 4 5 6 7...12

中文翻译

下载PDF

与HDMP-0482相关器件

型号	品牌	获取价格	描述	数据表
HDMP-0482G	PMC	获取价格	ATM/SONET/SDH Clock Recovery Circuit, PQFP64,
HDMP-0552	ETC	获取价格	AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA VALID DETECTION
HDMP1000	ETC	获取价格	Optoelectronic
HDMP-1000	AGILENT	获取价格	Telecom Circuit, 1-Func, Bipolar, CQFP68, CERAMIC, QFP-68
HDMP-1002	ETC	获取价格	Receiver
HDMP-1004	ETC	获取价格	Transmitter
HDMP-1012	AGILENT	获取价格	4Low Cost Gigabit Rate Transmit/Receive Chip Set
HDMP-1014	AGILENT	获取价格	4Low Cost Gigabit Rate Transmit/Receive Chip Set
HDMP-1022	AGILENT	获取价格	Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os
HDMP-1024	AGILENT	获取价格	Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os

与HDMP-0482相关文章

晶圆厂易主：Coherent公司2000万英镑出售苹果供应链关键资产
2024-10-08

5
Galaxy S25系列或全系搭载骁龙8 Elite
2024-10-08

3
三大厂商12层HBM3E进展迅速
2024-10-08

4
塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

41

产品中心

服务支持

精选活动

关于我们

帮助中心

HDMP-0482

HDMP-0482 技术参数

HDMP-0482 数据手册

与HDMP-0482相关器件

与HDMP-0482相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

HDMP-0482

HDMP-0482 技术参数

HDMP-0482 数据手册

与HDMP-0482相关器件

与HDMP-0482相关文章

您还可以找

您在本页遇到什么问题？