HDMP-0480

更新时间： 2024-10-03 23:14:59

品牌	Logo	应用领域
安捷伦 - AGILENT		电信集成电路电信电路时钟
页数	文件大小	规格书
11页	119K
描述
Octal Cell Port Bypass Circuit without Clock and Data Recovery

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中文翻译

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技术参数
数据手册

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HDMP-0480 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	FQFP, QFP64,.51SQ,20
针数：	64	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.77
Is Samacsys：	N	JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e0	长度：	10 mm
功能数量：	1	端子数量：	64
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装等效代码：	QFP64,.51SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, FINE PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	2.45 mm	子类别：	Other Telecom ICs
最大压摆率：	0.28 mA	标称供电电压：	3.3 V
表面贴装：	YES	技术：	BIPOLAR
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10 mm
Base Number Matches：	1

HDMP-0480 数据手册

Agilent HDMP-0480

Octal Cell Port Bypass Circuit

without Clock and Data Recovery

Data Sheet

Features

• Supports 1.0625 GBd fibre channel

operation

• Supports 1.25 GBd gigabit Ethernet

(GE) operation

• Octal cell PBC in one package

Description

Tx± differential outputs goes to

the HDMP- 0480’s FM_NODE[n]±

differential input pins. When the

“disk bypassed” mode is selected,

the disk drive is either absent or

non-functional and the loop

bypasses the hard disk.

• Valid amplitude detection on

FM_NODE[7] input

The HDMP-0480 is an Octal Cell

Port Bypass Circuit (PBC). This

device minimizes part count, cost

and jitter accumulation. Port

Bypass Circuits are used in hard

disk arrays constructed in Fibre

Channel Arbitrated Loop (FC-AL)

configurations. By using Port

Bypass Circuits, hard disks may

be pulled out or swapped while

other disks in the array are

available to the system.

• Equalizers on all inputs

• High speed LVPECL I/O

• Buffered Line Logic (BLL) outputs

(no external bias resistors

required)

The “disk bypassed” mode is

enabled by pulling the BYPASS[n]-

pin low. Leave BYPASS[n]-

floating to enable the “disk in

loop” mode. HDMP-0480’s may be

cascaded with other members of

the HDMP-04XX/HDMP-05XX

• 0.76 W typical power at Vcc=3.3V

• 64 Pin, 10 mm, low cost plastic QFP

package

Applications

• RAID, JBOD, BTS cabinets

A Port Bypass Circuit (PBC)

consists of multiple 2:1 multiplex- family through the FM_NODE and

• Four 2:1 muxes

ers daisy chained along with a

CDR. Each port has two modes of

operation: “disk in loop” and

“disk by-passed”. When the “disk

TO_NODE pins to accommodate

any number of hard disks. The

unused cells in this PBC may be

bypassed by using pulldown

• Four 1:2 buffers

• 1 = > N gigabit serial buffer

• N = > 1 gigabit serial mux

in loop” mode is selected, the loop resistors on the BYPASS[n]- pins

goes into and out of the disk drive for these cells.

at that port. For example, data

goes from the HDMP-0480’s

TO_NODE[n]± differential output

An HDMP-0480 may also be used

as eight 1:1 buffers. In addition,

pins to the Disk Drive Transceiver an HDMP-0480 may be config-

IC’s (e.g. an HDMP-1636A) Rx±

differential input pins. Data from

the Disk Drive Transceiver IC’s

ured as four 2:1 multiplexers or

as four 1:2 buffers.

HDMP-0480

CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and

assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).

12 3 4 5 6 7...11

中文翻译

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与HDMP-0480相关器件

型号	品牌	获取价格	描述	数据表
HDMP-0482	AGILENT	获取价格	Octal Cell Port Bypass Circuit with CDR and Data Valid Detection
HDMP-0482	HP	获取价格	Octal Cell Port Bypass Circuit with CDR and Data Valid Detection
HDMP-0482G	PMC	获取价格	ATM/SONET/SDH Clock Recovery Circuit, PQFP64,
HDMP-0552	ETC	获取价格	AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA VALID DETECTION
HDMP1000	ETC	获取价格	Optoelectronic
HDMP-1000	AGILENT	获取价格	Telecom Circuit, 1-Func, Bipolar, CQFP68, CERAMIC, QFP-68
HDMP-1002	ETC	获取价格	Receiver
HDMP-1004	ETC	获取价格	Transmitter
HDMP-1012	AGILENT	获取价格	4Low Cost Gigabit Rate Transmit/Receive Chip Set
HDMP-1014	AGILENT	获取价格	4Low Cost Gigabit Rate Transmit/Receive Chip Set

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