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HD74LV126ARP PDF预览

HD74LV126ARP

更新时间: 2024-09-15 23:55:27
品牌 Logo 应用领域
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页数 文件大小 规格书
11页 311K
描述
BUFFER/DRIVER|SINGLE|4-BIT|LV-CMOS|SOP|14PIN|PLASTIC

HD74LV126ARP 数据手册

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HD74LV126A  
Quad. Bus Buffer Gates with 3-state Outputs  
ADE-205-259 (Z)  
1st Edition  
March 1999  
Description  
The HD74LV126A features independent line drivers with three state outputs. Each output is disabled when  
the associated output enable (OE) input is low. To ensure the high impedance state during power up or power  
down, OE should be connected to GND through a pull-down resistor; the minimum value of the resistor is  
determined by the current souring capability of the driver. Low-voltage and high-speed operation is suitable  
for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the  
battery life.  
Features  
VCC = 2.0 V to 5.5 V operation  
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)  
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)  
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)  
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)  
Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V)  
Function Table  
Inputs  
OE  
H
A
H
L
Output Y  
H
L
H
L
X
Z
Note: H:High level  
L:Low level  
X:Immaterial  
Z:High impedance  

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