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HD74HCT563P PDF预览

HD74HCT563P

更新时间: 2024-11-21 23:55:27
品牌 Logo 应用领域
其他 - ETC 逻辑集成电路光电二极管驱动
页数 文件大小 规格书
11页 68K
描述
LATCH|SINGLE|8-BIT|HCT-CMOS|DIP|20PIN|PLASTIC

HD74HCT563P 数据手册

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HD74HCT563/HD74HCT573  
Octal Transparent Latches (with 3-state outputs)  
Description  
When the latch enable (LE) input is high, the Q outputs of HD74HCT563 will follow the inversion of the D  
inputs and the Q outputs of HD74HCT573 will follow the D inputs.  
When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enabled  
returns high again. When a high logic level is applied to the output control input, all outputs go to a high  
impedance state, regardless of what signals are present at the other inputs and the state of the storage  
elements.  
Features  
LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility  
High Speed Operation: tpd (D to Q, Q) = 13 ns typ (CL = 50 pF)  
High Output Current: Fanout of 15 LSTTL Loads  
Wide Operating Voltage: VCC = 4.5 to 5.5 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Function Table  
Outputs  
Output Control  
Latch Enable  
Data  
H
HD74HCT563  
HD74HCT573  
L
L
L
H
H
H
L
L
H
L
L
H
Q0  
Z
X
Q0  
Z
X
X

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