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HD74HCT564RPEL PDF预览

HD74HCT564RPEL

更新时间: 2024-11-22 05:35:15
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瑞萨 - RENESAS 触发器
页数 文件大小 规格书
9页 116K
描述
Octal D-type Flip-Flops (with 3-state outputs)

HD74HCT564RPEL 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:5.13
系列:HCTJESD-30 代码:R-PDSO-G20
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:24000000 Hz
最大I(ol):0.006 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):225电源:5 V
传播延迟(tpd):39 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.5 mm
Base Number Matches:1

HD74HCT564RPEL 数据手册

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HD74HCT564, HD74HCT574  
Octal D-type Flip-Flops (with 3-state outputs)  
REJ03D0670–0200  
(Previous ADE-205-560)  
Rev.2.00  
Mar 30, 2006  
Description  
These devices are positive edge triggered flip-flops. The difference between HD74HCT564 and HD74HCT574 is only  
that the former has inverting outputs and the latter has noninvertering outputs.  
Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs on positive  
going transitions of the clock (CK) input. when a high logic level is applied to the output control (OC) input, all outputs  
go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage  
elements.  
Features  
LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility  
High Speed Operation: tpd (D to Q, Q) = 15 ns typ (CL = 50 pF)  
High Output Current: Fanout of 15 LSTTL Loads  
Wide Operating Voltage: VCC = 4.5 to 5.5 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-20 pin  
HD74HCT564P  
PRDP0020AC-B  
(DP-20NEV)  
P
HD74HCT574P  
HD74HCT564FPEL  
HD74HCT574FPEL  
HD74HCT564RPEL  
HD74HCT574RPEL  
PRSP0020DD-B  
(FP-20DAV)  
SOP-20 pin (JEITA)  
SOP-20 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (1,000 pcs/reel)  
PRSP0020DC-A  
(FP-20DBV)  
Note: Please consult the sales office for the above package availability.  
Function Table  
Inputs  
Outputs  
Output Control  
Clock  
Data  
H
HD74HCT564  
HD74HCT574  
L
L
L
H
H
L
L
L
L
X
Q0  
Z
Q0  
Z
H
X
X
Q0 : level of Q before the indicated Steady-sate input conditions were established.  
Q0 : complement of Q0 or level of Q before the indicated Steady-state input Conditions were established.  
Rev.2.00 Mar 30, 2006 page 1 of 8  

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