Datasheet > HD74HC76RP

HD74HC76RP

更新时间： 2024-09-28 19:57:15

品牌	Logo	应用领域
日立 - HITACHI		光电二极管逻辑集成电路触发器
页数	文件大小	规格书
8页	51K
描述
J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, FP-16DN

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HD74HC76RP 数据手册

HD74HC76

Dual J-K Flip-Flops (with Preset and Clear)

Description

Each flip-flop has independent J, K, preset, clear, and clock inputs and Q and Q outputs. This device is

edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear

and preset are independent of the clock and accomplished by a low logic level on the corresponding input.

Features

•

High Speed Operation: t_pd(Clock to Q) = 21 ns typ (C_L= 50 pF)

High Output Current: Fanout of 10 LSTTL Loads

Wide Operating Voltage: V_CC= 2 to 6 V

Low Input Current: 1 µA max

Low Quiescent Supply Current: I_CC(static) = 2 µA max (Ta = 25°C)

Function Table

Inputs

Outputs

Preset

Clear

Clock

H*¹

No change

Toggle

No change

Note: 1. Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable,

if Preset and Clear go HIGH simultaneously.

12 3 4 5 6 7 8

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型号	品牌	获取价格	描述	数据表
HD74HC76RP-EL	HITACHI	获取价格	J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output,
HD74HC77	HITACHI	获取价格	4-bit Bistable Latch
HD74HC77	RENESAS	获取价格	4-bit Bistable Latch
HD74HC77FP	ETC	获取价格	LATCH\|SINGLE\|4-BIT\|HC-CMOS\|SOP\|14PIN\|PLASTIC
HD74HC77FP-E	RENESAS	获取价格	HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO14, FP-14DA
HD74HC77FPEL	RENESAS	获取价格	4-bit Bistable Latch
HD74HC77FP-EL	HITACHI	获取价格	D Latch, HC/UH Series, 2-Func, High Level Triggered, 2-Bit, True Output, CMOS, PDSO14, FP-
HD74HC77FP-EL	RENESAS	获取价格	HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO14, FP-14DA
HD74HC77P	RENESAS	获取价格	4-bit Bistable Latch
HD74HC77RP	ETC	获取价格	LATCH\|SINGLE\|4-BIT\|HC-CMOS\|SOP\|14PIN\|PLASTIC