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HD74HC78T-EL PDF预览

HD74HC78T-EL

更新时间: 2024-01-27 05:42:47
品牌 Logo 应用领域
瑞萨 - RENESAS 触发器时钟
页数 文件大小 规格书
7页 106K
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HD74HC78T-EL 数据手册

 浏览型号HD74HC78T-EL的Datasheet PDF文件第2页浏览型号HD74HC78T-EL的Datasheet PDF文件第3页浏览型号HD74HC78T-EL的Datasheet PDF文件第4页浏览型号HD74HC78T-EL的Datasheet PDF文件第5页浏览型号HD74HC78T-EL的Datasheet PDF文件第6页浏览型号HD74HC78T-EL的Datasheet PDF文件第7页 
HD74HC78  
Dual J-K Flip-Flops  
(with Preset, Common Clear and Common Clock)  
REJ03D0553-0200  
(Previous ADE-205-425)  
Rev.2.00  
Oct 06, 2005  
Description  
This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each  
flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are controlled by a common clear  
and a common clock. Preset and clear are independent of the clock and accomplished by a low logic level on the  
corresponding input.  
Features  
High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
SOP-14 pin (JEITA)  
SOP-14 pin (JEDEC)  
PRSP0014DF-B  
(FP-14DAV)  
HD74HC78FPEL  
HD74HC78RPEL  
FP  
RP  
EL (2,000 pcs/reel)  
PRSP0014DE-A  
(FP-14DNV)  
EL (2,500 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Function Table  
Inputs  
Outputs  
Preset  
Clear  
H
Clock  
J
X
X
X
L
K
X
X
X
L
Q
Q
L
L
H
L
X
X
X
H
L
L
H*1  
H
H*1  
L
H
H
H
H
H
H
H
H
No change  
L
H
L
H
L
H
L
H
H
H
X
X
X
H
H
H
X
X
X
Toggle  
No change  
No change  
No change  
H
L
H
H
H
H :  
L :  
X :  
High level  
Low level  
Irrelevant  
Note: 1. Q and Q will remain High as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and  
Clear go High simultaneously.  
Rev.2.00, Oct 06, 2005 page 1 of 6  

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