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HD74HC78P PDF预览

HD74HC78P

更新时间: 2024-09-28 20:04:47
品牌 Logo 应用领域
日立 - HITACHI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
10页 58K
描述
J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP14, DP-14

HD74HC78P 数据手册

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HD74HC78  
Dual J-K Flip-Flops (with Preset, Common Clear and  
Common Clock)  
Description  
This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock  
pulse. Each flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are  
controlled by a common clear and a common clock. Preset and clear are independent of the clock and  
accomplished by a low logic level on the corresponding input.  
Features  
High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)  

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