Datasheet > HD74HC74T-EL

HD74HC74T-EL

更新时间： 2024-01-10 13:43:50

品牌	Logo	应用领域
日立 - HITACHI		光电二极管逻辑集成电路触发器
页数	文件大小	规格书
9页	55K
描述
HC/UH SERIES, D FLIP-FLOP, PDSO14, TTP-14D

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HD74HC74T-EL 数据手册

HD74HC74

Dual D-type Flip-Flops (with Preset and Clear)

Description

The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level

present at thte data input is transferred to the output during the positive going transition to the clock pulse.

Preset and clear are independent of the clock and accomplished by a low level at the appropriate input.

Features

•

High Speed Operation: t_pd(Clock to Q or Q) = 14 ns typ (C_L= 50 pF)

High Output Current: Fanout of 10 LSTTL Loads

Wide Operating Voltage: V_CC= 2 to 6 V

Low Input Current: 1 µA max

Low Quiescent Supply Current: I_CC(static) = 2 µA max (Ta = 25°C)

Function Table

Inputs

Outputs

Preset

Clear

Clock

Data

H*¹

no change

Note: 1. Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable,

if Preset and Clear go HIGH simultaneously.

12 3 4 5 6 7...9

中文翻译

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型号	品牌	获取价格	描述	数据表
HD74HC74TELL	RENESAS	获取价格	Dual D-type Flip-Flops (with Preset and Clear)
HD74HC75	RENESAS	获取价格	Quad. Bistable Latches
HD74HC75	HITACHI	获取价格	Quad. Bistable Latches
HD74HC75FP	ETC	获取价格	LATCH\|DUAL\|2-BIT\|HC-CMOS\|SOP\|16PIN\|PLASTIC
HD74HC75FP-E	RENESAS	获取价格	HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16, FP-16DA
HD74HC75FPEL	RENESAS	获取价格	Quad. Bistable Latches
HD74HC75P	RENESAS	获取价格	Quad. Bistable Latches
HD74HC75P-E	RENESAS	获取价格	HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16, 6.30 X 19.2
HD74HC75RP	RENESAS	获取价格	HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16, FP-16DN
HD74HC75RPEL	RENESAS	获取价格	Quad. Bistable Latches