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HD74HC4020P PDF预览

HD74HC4020P

更新时间: 2024-11-19 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 94K
描述
14-stage Binary Counter

HD74HC4020P 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Not Recommended零件包装代码:DIP
包装说明:6.30 X 19.20 MM, 2.54 MM PITCH, PLASTIC, DIP-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:5.09
Is Samacsys:N计数方向:UP
系列:HC/UHJESD-30 代码:R-PDIP-T16
长度:19.2 mm负载电容(CL):50 pF
负载/预设输入:NO逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:20000000 Hz最大I(ol):0.004 A
工作模式:ASYNCHRONOUS湿度敏感等级:1
位数:14功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
传播延迟(tpd):220 ns认证状态:Not Qualified
座面最大高度:5.06 mm子类别:Counters
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:7.62 mm
Base Number Matches:1

HD74HC4020P 数据手册

 浏览型号HD74HC4020P的Datasheet PDF文件第2页浏览型号HD74HC4020P的Datasheet PDF文件第3页浏览型号HD74HC4020P的Datasheet PDF文件第4页浏览型号HD74HC4020P的Datasheet PDF文件第5页浏览型号HD74HC4020P的Datasheet PDF文件第6页浏览型号HD74HC4020P的Datasheet PDF文件第7页 
HD74HC164  
8-bit Parallel-out Shift Register  
REJ03D0580-0300  
Rev.3.00  
Jan 31, 2006  
Description  
This 8-bit shift register has gated serial inputs and clear. Each register bit is a D-type master/slave flip-flop. Inputs A  
& B permit complete control over the incoming data. A low at either or both inputs inhibits entry of new data and  
resets the first flip-flop to the low level at the next clock pulse. A high level on the input enables the other input which  
will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or  
low, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and  
out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and  
accomplished by a low level at the clear input.  
Features  
High Speed Operation: tpd (Clock to Q) = 14.5 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
HD74HC164P  
HD74HC164FPEL SOP-14 pin (JEITA)  
Package Type  
PRDP0014AB-B  
(DP-14AV)  
DILP-14 pin  
P
PRSP0014DF-B  
(FP-14DAV)  
FP  
EL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Function Table  
Inputs  
Outputs  
·········  
·········  
·········  
·········  
·········  
·········  
Clear  
Clock  
A
X
X
L
B
X
X
X
L
QA  
L
QB  
L
QH  
L
L
H
H
H
H
X
QAo  
L
QBo  
QAn  
QAn  
QAn  
QHo  
QGn  
QGn  
QGn  
X
H
L
H
H
QAo to QHo = Outputs remain unchanged.  
An to QGn = Data shifted from the previous stage on a positive edge at the clock input.  
Q
H :  
L :  
X :  
High level  
Low level  
Irrelevant  
Rev.3.00, Jan 31, 2006 page 1 of 6  

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