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HD74HC4024 PDF预览

HD74HC4024

更新时间: 2024-11-19 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器
页数 文件大小 规格书
7页 91K
描述
7-stage Binary Counter

HD74HC4024 数据手册

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HD74HC4024  
7-stage Binary Counter  
REJ03D0325-0300  
Rev.3.00  
Mar 30, 2006  
Description  
The HD74HC4024 is a 7-stage counter. This device is incremented on the falling edge (negative transition) of the input  
clock, and all its output is reset to a low level by applying a logical high on its reset input.  
Features  
High Speed Operation: tpd (Clock to Q1) = 14 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-14 pin  
(Previous Code)  
PRDP0014AB-B  
(DP-14AV)  
HD74HC4024P  
P
PRSP0014DF-B  
(FP-14DAV)  
HD74HC4024FPEL  
HD74HC4024RPEL  
SOP-14 pin (JEITA)  
SOP-14 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0014DE-A  
(FP-14DNV)  
Note: Please consult the sales office for the above package availability.  
Function Table  
Clock  
L
Reset  
Outputs State  
L
H
L
No change  
L
All outputs are low  
No change  
H
H
H
L
All outputs are low  
No change  
H
L
All outputs are low  
Advance to next state  
All outputs are low  
H
Rev.3.00 Mar 30, 2006 page 1 of 6  

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