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HD74HC4024RP PDF预览

HD74HC4024RP

更新时间: 2024-11-18 23:55:27
品牌 Logo 应用领域
其他 - ETC 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 48K
描述
COUNTER|UP|7-BIT BINARY|HC-CMOS|SOP|14PIN|PLASTIC

HD74HC4024RP 数据手册

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HD74HC4024  
7-stage Binary Counter  
Description  
The HD74HC4024 is a 7-stage counter. This device is incremented on the falling edge (negative transition)  
of the input clock, and all its output is reset to a low level by applying a logical high on its reset input.  
Features  
High Speed Operation: tpd (Clock to Q1) = 14 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Function Table  
Clock  
Reset  
Outputs State  
No change  
L
L
L
H
L
All outputs are low  
No change  
H
H
H
L
All outputs are low  
No change  
H
L
All outputs are low  
Advance to next state  
All outputs are low  
H

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暂无描述
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