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HD74HC4040 PDF预览

HD74HC4040

更新时间: 2024-11-19 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器
页数 文件大小 规格书
7页 93K
描述
12-stage Binary Counter

HD74HC4040 数据手册

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HD74HC4040  
12-stage Binary Counter  
REJ03D0647-0200  
(Previous ADE-205-534)  
Rev.2.00  
Mar 30, 2006  
Description  
The HD74HC4040 is a 12-stage counter. This device is incremented on the falling edge (negative transition) of the  
input clock, and all its output is reset to a low level by applying a logical high on its reset input.  
Features  
High Speed Operation: tpd (Clock to Q1) = 15 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
HD74HC4040P  
HD74HC4040FPEL  
Package Type  
DILP-16 pin  
SOP-16 pin (JEITA)  
(Previous Code)  
PRDP0016AE-B  
(DP-16FV)  
P
PRSP0016DH-B  
(FP-16DAV)  
FP  
EL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Function Table  
C
Reset  
Outputs State  
L
L
No change  
Advance to next stage  
All outputs are low  
X
H
X: Irrelevant  
Rev.2.00 Mar 30, 2006 page 1 of 6  

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