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HD74HC4024FP-EL PDF预览

HD74HC4024FP-EL

更新时间: 2024-11-19 13:08:19
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器
页数 文件大小 规格书
7页 91K
描述
HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 7-BIT UP BINARY COUNTER, PDSO14, FP-14DA

HD74HC4024FP-EL 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:14
Reach Compliance Code:unknown风险等级:5.31
Is Samacsys:N计数方向:UP
系列:HC/UHJESD-30 代码:R-PDSO-G14
长度:10.06 mm负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER工作模式:ASYNCHRONOUS
位数:7功能数量:1
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):230 ns
认证状态:Not Qualified座面最大高度:2.2 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL触发器类型:NEGATIVE EDGE
宽度:5.5 mmBase Number Matches:1

HD74HC4024FP-EL 数据手册

 浏览型号HD74HC4024FP-EL的Datasheet PDF文件第2页浏览型号HD74HC4024FP-EL的Datasheet PDF文件第3页浏览型号HD74HC4024FP-EL的Datasheet PDF文件第4页浏览型号HD74HC4024FP-EL的Datasheet PDF文件第5页浏览型号HD74HC4024FP-EL的Datasheet PDF文件第6页浏览型号HD74HC4024FP-EL的Datasheet PDF文件第7页 
HD74HC4024  
7-stage Binary Counter  
REJ03D0325-0300  
Rev.3.00  
Mar 30, 2006  
Description  
The HD74HC4024 is a 7-stage counter. This device is incremented on the falling edge (negative transition) of the input  
clock, and all its output is reset to a low level by applying a logical high on its reset input.  
Features  
High Speed Operation: tpd (Clock to Q1) = 14 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-14 pin  
(Previous Code)  
PRDP0014AB-B  
(DP-14AV)  
HD74HC4024P  
P
PRSP0014DF-B  
(FP-14DAV)  
HD74HC4024FPEL  
HD74HC4024RPEL  
SOP-14 pin (JEITA)  
SOP-14 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0014DE-A  
(FP-14DNV)  
Note: Please consult the sales office for the above package availability.  
Function Table  
Clock  
L
Reset  
Outputs State  
L
H
L
No change  
L
All outputs are low  
No change  
H
H
H
L
All outputs are low  
No change  
H
L
All outputs are low  
Advance to next state  
All outputs are low  
H
Rev.3.00 Mar 30, 2006 page 1 of 6  

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