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HD74AC273RPEL PDF预览

HD74AC273RPEL

更新时间: 2024-10-31 05:35:11
品牌 Logo 应用领域
瑞萨 - RENESAS 触发器
页数 文件大小 规格书
8页 118K
描述
Octal D-Type Flip-Flop

HD74AC273RPEL 数据手册

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HD74AC273  
Octal D-Type Flip-Flop  
REJ03D0265–0200Z  
(Previous ADE-205-386 (Z))  
Rev.2.00  
Jul.16.2004  
Description  
The HD74AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common  
buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.  
The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition,  
is transferred to the corresponding flip-flops’s Q output  
All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the MR input. The  
device is useful for applications where the true output only is required and the Clock and Master Reset are common to  
all storage elements.  
Features  
Ideal Buffer for MOS Microprocessor or Memory  
Eight Edge-Triggered D Flip-Flops  
Buffered Common Clock  
Buffered, Asynchronous Master Reset  
See HD74AC373 for Transparent Latch Version  
See HD74AC374 for 3-State Version  
Outputs Source/Sink 24 mA  
Ordering Information  
Part Name  
HD74AC273P  
Package Type  
DIP-20 pin  
Package Code Package Abbreviation Taping Abbreviation (Quantity)  
DP-20N  
P
HD74AC273FPEL SOP-20 pin (JEITA) FP-20DAV  
HD74AC273RPEL SOP-20 pin (JEDEC) FP-20DBV  
FP  
RP  
EL (2,000 pcs/reel)  
EL (1,000 pcs/reel)  
Notes: 1. Please consult the sales office for the above package availability.  
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of  
the package code.  
Rev.2.00, Jul.16.2004, page 1 of 7  

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