Datasheet > HD74AC273T-EL

HD74AC273T-EL

更新时间： 2024-11-01 20:49:55

品牌	Logo	应用领域
日立 - HITACHI		光电二极管逻辑集成电路触发器
页数	文件大小	规格书
10页	58K
描述
D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20, TTP-20DA

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HD74AC273T-EL 数据手册

HD74AC273

Octal D Flip-Flop

Description

The HD74AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The

common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops

simultaneously.

The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High

clock transition, is transferred to the corresponding flip-flops’s Q output

All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the MR

input. The device is useful for applications where the true output only is required and the Clock and Master

Reset are common to all storage elements.

Features

•

Ideal Buffer for MOS Microprocessor or Memory

Eight Edge-Triggered D Flip-Flops

Buffered Common Clock

Buffered, Asynchronous Master Reset

See HD74AC373 for Transparent Latch Version

See HD74AC374 for 3-State Version

Outputs Source/Sink 24 mA

12 3 4 5 6 7...10

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型号	品牌	获取价格	描述	数据表
HD74AC273T-ELL	RENESAS	获取价格	D FLIP-FLOP, PDSO20, TTP-20DA
HD74AC280	RENESAS	获取价格	9-bit Parity Generator/Checker
HD74AC280	HITACHI	获取价格	9-bit Parity Generator/Checker
HD74AC280/HD74ACT280	ETC	获取价格
HD74AC280FP	RENESAS	获取价格	AC SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14, FP-14DA
HD74AC280FPEL	RENESAS	获取价格	9-bit Parity Generator/Checker
HD74AC280FP-EL	RENESAS	获取价格	AC SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14, SOP-14
HD74AC280FPVEL	RENESAS	获取价格	暂无描述
HD74AC280P	ETC	获取价格	Parity Generator/Checker
HD74AC280RPEL	RENESAS	获取价格	9-bit Parity Generator/Checker