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HD74AC280FP-EL PDF预览

HD74AC280FP-EL

更新时间: 2024-11-05 12:58:35
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
8页 210K
描述
AC SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14, SOP-14

HD74AC280FP-EL 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:14
Reach Compliance Code:unknown风险等级:5.51
Is Samacsys:N其他特性:ALSO OPERATES WITH 5V SUPPLY
系列:ACJESD-30 代码:R-PDSO-G14
长度:10.06 mm逻辑集成电路类型:PARITY GENERATOR/CHECKER
位数:9功能数量:1
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
传播延迟(tpd):18.5 ns认证状态:Not Qualified
座面最大高度:2.2 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:5.5 mmBase Number Matches:1

HD74AC280FP-EL 数据手册

 浏览型号HD74AC280FP-EL的Datasheet PDF文件第2页浏览型号HD74AC280FP-EL的Datasheet PDF文件第3页浏览型号HD74AC280FP-EL的Datasheet PDF文件第4页浏览型号HD74AC280FP-EL的Datasheet PDF文件第5页浏览型号HD74AC280FP-EL的Datasheet PDF文件第6页浏览型号HD74AC280FP-EL的Datasheet PDF文件第7页 
HD74AC280  
9-bit Parity Generator/Checker  
REJ03D0266–0200Z  
(Previous ADE-205-387 (Z))  
Rev.2.00  
Jul.16.2004  
Description  
The HD74AC280 is a high-speed parity generator/checker that accepts nine bits of input data and detects whether an  
even or an odd number of these inputs is High. If an even number of inputs is High, the Sum Even output is High. If an  
odd number is High, the Sum Even output is Low. The Sum Odd output is the complement of the Sum Even output.  
Features  
Outputs Source/Sink 24 mA  
Ordering Information  
Part Name  
Package Type  
Package Code Package breviation (Quantity)  
HD74AC280FPEL SOP-14 pin (JEITA) FP-14DAV  
HD74AC280RPEL SOP-14 pin (JEDEC) FP-14DNV  
FP  
RP  
s/reel)  
pcs/reel)  
Notes: 1. Please consult the sales office for the above pack
2. The packages with lead-free pins are distinguisucts by adding V at the end of  
the package code.  
Pin Arrangement  
5
6
14 VCC  
13 I  
5
4
3
2
1
0
12  
11  
I
I
10 I  
Σ
O
9
8
I
I
GND 7  
(Top view)  
Rev.2.00, Jul.16.2004, page 1 of 7  

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