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HCTS160DTR PDF预览

HCTS160DTR

更新时间: 2024-11-01 22:49:35
品牌 Logo 应用领域
英特矽尔 - INTERSIL 计数器触发器逻辑集成电路
页数 文件大小 规格书
3页 95K
描述
Radiation Hardened Synchronous Counter

HCTS160DTR 数据手册

 浏览型号HCTS160DTR的Datasheet PDF文件第2页浏览型号HCTS160DTR的Datasheet PDF文件第3页 
HCTS160T  
Data Sheet  
July 1999  
File Number 4626.1  
Radiation Hardened Synchronous  
Counter  
Features  
• QML Class T, Per MIL-PRF-38535  
Intersil’s Satellite Applications FlowTM (SAF) devices are fully  
tested and guaranteed to 100kRAD total dose. These QML  
Class T devices are processed to a standard flow intended  
to meet the cost and shorter lead-time needs of large  
volume satellite manufacturers, while maintaining a high  
level of reliability.  
• Radiation Performance  
5
- Gamma Dose (γ) 1 x 10 RAD(Si)  
- Latch-Up Free Under Any Conditions  
2
- SEP Effective LET No Upsets: >100 MEV-cm /mg  
-9  
- Single Event Upset (SEU) Immunity < 2 x 10  
Errors/Bit-Day (Typ)  
The Intersil HCTS160T is a Radiation Hardened High Speed  
Presettable BCD Decade Synchronous Counter that  
features an asynchronous reset and look-ahead carry logic.  
Counting and parallel presetting are accomplished  
• 3 Micron Radiation Hardened SOS CMOS  
• Fanout (Over Temperature Range)  
- Standard Outputs 10 LSTTL Loads  
synchronously with the low-to-high transition of the clock. A  
low level on the synchronous parallel enable input, SPE,  
disables counting and allows data at the preset inputs, P0 -  
P3, to be loaded into the counter. The counter is reset by a  
low on the master reset input, MR. Two count enables, PE  
and TE are provided for n-bit cascading. TE also controls the  
terminal count output, TC. The terminal count output  
indicates a maximum count for one clock pulse and is used  
to enable the next cascaded stage to count.  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
• LSTTL Input Compatibility  
- V = 0.8V Max  
IL  
- V = V  
IH  
Min  
CC/2  
• Input Current Levels Ii 5mA at V , V  
OL OH  
Pinouts  
Specifications  
HCTS160DTR (SBDIP), CDIP2-T16  
TOP VIEW  
Specifications for Rad Hard QML devices are controlled by  
the Defense Supply Center in Columbus (DSCC). The SMD  
numbers listed below must be used when ordering.  
MR  
CP  
P0  
1
2
3
4
5
6
7
8
16 V  
CC  
15 TC  
14 Q0  
13 Q1  
12 Q2  
11 Q3  
10 TE  
Detailed Electrical Specifications for the HCTS160T are  
contained in SMD 5962-95742. A “hot-link” is provided from  
our website for downloading.  
P1  
P2  
www.intersil.com/spacedefense/newsafclasst.asp  
P3  
Intersil‘s Quality Management Plan (QM Plan), listing all  
Class T screening operations, is also available on our  
website.  
PE  
9
SPE  
GND  
www.intersil.com/quality/manuals.asp  
HCTS160KTR (FLATPACK), CDFP4-F16  
Ordering Information  
TOP VIEW  
TEMP.  
ORDERING  
NUMBER  
RANGE  
( C)  
MR  
CP  
P0  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
CC  
o
PART NUMBER  
HCTS160DTR  
HCTS160KTR  
TC  
Q0  
Q1  
Q2  
Q3  
TE  
5962R9574201TEC  
5962R9574201TXC  
-55 to 125  
-55 to 125  
P1  
P2  
NOTE: Minimum order quantity for -T is 150 units through  
distribution, or 450 units direct.  
P3  
PE  
GND  
SPE  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
1
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.  

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