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HCF4099 PDF预览

HCF4099

更新时间: 2024-11-03 22:57:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 锁存器双倍数据速率
页数 文件大小 规格书
14页 305K
描述
8-BIT ADDRESSABLE LATCH

HCF4099 数据手册

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HCC/HCF4099B  
8-BIT ADDRESSABLE LATCH  
.
.
SERIAL DATA INPUT - ACTIVE PARALLEL  
OUTPUT  
STORAGE REGISTER CAPABILITY - MASTER  
CLEAR  
CAN FUNCTION AS DEMULTIPLEXER  
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
5V, 10V, AND 15V PARAMETRIC RATINGS  
INPUT CURRENT OF100nA AT 18V AND 25°C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVE STANDARD N°. 13A, ”STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
.
.
EY  
F
.
Plastic Package  
Ceramic Frit Seal Package  
.
.
.
.
M1  
C1  
Micro Package  
Plastic Chip Carrier  
ORDER CODES :  
HCC4099BF  
HCF4099BM1  
HCF4099BEY  
HCF4099BC1  
PIN CONNECTIONS  
DESCRIPTION  
The HCC4099B (extended temperature range) and  
HCF4099B (intermediate temperature range) are  
monolithic integratedcircuits, available in16-lead dual  
in-line plastic or ceramic package and plastic micro  
package. The HCC/HCF4099B 8-bit addressable  
latchisaserial-input, parallel-output storage register  
that can perform a variety of functions. Data are in-  
putted to a particular bit in the latch when that bit is  
addressed (by means of inputs A0, A1, A2) and  
when WRITE DISABLE is at a low level. When  
WRITE DISABLE is high, data entry is inhibited ;  
however, all 8 outputs can be continuously read in-  
dependent of WRITE DISABLE and address inputs.  
A master RESET input is available, which resets all  
bits to a logic ”0” level when RESET and WRITE  
DISABLE are at a high level. When RESET is at a  
high level, and WRITE DISABLE is at a low level, the  
latch acts as a 1-of-8 demultiplexer ; the bit that is  
addressed has an active output which follows the  
data input, while all unaddressed bits are held to a  
logic ”0” level.  
September 1988  
1/14  

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