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HCF4027BC1 PDF预览

HCF4027BC1

更新时间: 2024-10-26 22:22:31
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路
页数 文件大小 规格书
12页 288K
描述
DUAL-J-K MASTER-SLAVE FLIP-FLOP

HCF4027BC1 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.83
Is Samacsys:N系列:4000/14000/40000
JESD-30 代码:S-PQCC-J20JESD-609代码:e3
长度:8.965 mm负载电容(CL):50 pF
逻辑集成电路类型:J-K FLIP-FLOP最大频率@ Nom-Sup:3500000 Hz
位数:2功能数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/15 V传播延迟(tpd):300 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:8.965 mm
最小 fmax:3.5 MHzBase Number Matches:1

HCF4027BC1 数据手册

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HCC/HCF4027B  
DUAL-J-K MASTER-SLAVE FLIP-FLOP  
.
.
SET-RESET CAPABILITY  
STATIC FLIP-FLOP OPERATION - RETAINS  
STATE INDEFINITELY WITH CLOCK LEVEL  
EITHER ”HIGH” OR ”LOW”  
MEDIUM SPEED OPERATION - 16MHz (typ.  
clock toggle rate at 10V)  
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVE STANDARD N0. 13A, ”STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”.  
.
.
.
.
F
EY  
(Plastic Package)  
(Ceramic Frit Seal Package)  
.
.
M1  
C1  
(Micro Package)  
(Plastic Chip Carrier)  
ORDER CODES :  
HCC4027BF  
HCF4027BEY  
HCF4027BM1  
HCF4027BC1  
PIN CONNECTIONS  
DESCRIPTION  
The HCC4027B (extended temperature range) and  
HCF4027B (intermediate temperature range) are  
monolithic integrated circuit, available in 16-lead  
dual in-line plastic or ceramic package and plastic  
micro package.  
The HCC/HCF4027B is a single monolithic chip in-  
tegratedcircuit containing twoidentical complemen-  
tary-symmetry J-K master-slave flip-flops. Each  
flip-flop has provisions for individual J, K, Set, Reset,  
and Clock input signals, Buffered Q and Q signals  
are provided as outputs. This input-output arrange-  
ment provides for compatible operation with the  
HCC/HCF4013B dual D-type flip-flop.  
TheHCC/HCF4027B isuseful in performing control,  
register, and toggle functions. Logic levels present  
at the J and K inputs along with internal self-steering  
control thestateof each flip-flop ; changes in theflip-  
flop state are synchronous with the positive-going  
transition of the clock pulse. Set and reset functions  
are independent of the clock and are initiated when  
a high level signal is present at either the Set or  
Reset input.  
June 1989  
1/12  

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